ics9248-153 Integrated Device Technology, ics9248-153 Datasheet
ics9248-153
Related parts for ics9248-153
ics9248-153 Summary of contents
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... ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9248-153 1 48 VDDREF ...
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... ICS9248-153 Pin Descriptions ...
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... ICS9248-153 PWD 0 AGP 66.67 63.33 67.33 76.67 67.13 68.67 70.00 73.33 68.00 69.33 70.67 71.33 72.00 72.67 01000 60.00 Note1 74.00 74.67 75.33 76.00 77.33 78.00 78.67 79.33 60.00 71.00 72.00 73.00 69.00 68.00 67.50 70.00 75. ...
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... ICS9248-153 Command Bitmaps Byte 4: Clock Control Register ...
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... Select @ 100 MHz pF; Select @ 133 MHz pF; Input address to VDD or GND 3 Logic Inputs X1 & X2 pins From target frequency 50%, CPU=100MHz 50%, CPU=100MHz T 5 ICS9248-153 +0.5 V MIN TYP MAX -0.3 0 -200 180 180 600 12 14.318 16 5 ...
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... ICS9248-153 Electrical Characteristics - USB, REF 70º 3.3 V +/- 5 PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter, Cycle-to-Cycle, REF Jitter, Cycle-to-Cycle, fixed clock 1 Guaranteed by design, not 100% tested in production. ...
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... (unless otherwise stated). L CONDITIONS 2. ICS9248-153 MIN TYP MAX UNITS 2.6 V 0 320 500 ps 88 500 ps MIN TYP MAX UNITS 2.6 V 0.4 V -12 ...
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... ICS9248-153 Electrical Characteristics - AGP 70º 3.3 V +/- 5 PARAMETER SYMBOL Output High Voltage V OH4B Output Low Voltage V OL4B I Output High Current OH4B I Output Low Current OL4B 1 Rise Time t r4B 1 Fall Time t f4B 1 Duty Cycle d t4B 1 Skew (window) t sk4B t Jitter, Cycle-to-Cycle ...
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... ACK ACK ACK ACK ACK 2 C component. It can read back the data stored in the latches for 2 C interface, the protocol is set to use only "Block-Writes" from the controller. The 9 ICS9248-153 2 C programming. How to Read: ICS (Slave/Receiver) Start Bit Address D3 (H) ACK Byte Count ...
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... ICS9248-153 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS9248- 153 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function ...
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... General Description The ICS9248-153 is a main clock synthesizer chip for AMD-K7 based systems. This provides all clocks required for such a system when used with a Zero Delay Buffer Chip such as the ICS9179-06. Spread spectrum may be enabled through I 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-153 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations ...
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... ICS9248-153 PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-153 used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-153 internally. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed. PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock ...
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... Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-153 device shown, the outputs Stop Low on the next falling edge after PD# goes low asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. ...
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... ICS9248-153 INDEX INDEX AREA AREA 45° 45° SEATING SEATING b PLANE PLANE .10 (.004) C .10 (.004) C 300 mil SSOP Package Ordering Information ICS9248yF-153-T Example: ICS XXXX PPP - T Designation for tape and reel packaging Pattern Number ( digit number for parts with ROM code patterns) ...