ics9248-199 Integrated Device Technology, ics9248-199 Datasheet
ics9248-199
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ics9248-199 Summary of contents
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... These are double strength. 35.66 71.33 53.50 ** (1X/2X) have single or double strength to 36.66 73.33 55.00 drive 2 loads. 36.66 73.33 55.00 36.66 73.33 55.00 1. Internal pull-up, of 120K to V 31.25 66.68 55.57 2. These inputs have a 120K pull down to GND. 33.33 66.66 50.00 ICS9248-199 2 C Index read/write and block read/write 1 48 VDDLAPIC REF0 2 47 IOAPIC GND GND 4 45 VDDL GND 5 44 CPUCLKT0 X1 6 ...
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... ICS9248-199 Pin Configuration PIN NUMBER PIN NAME 1, 11, 17, 21, 25, VDD 36 FS0 2 REF0 FS1 3 REF1 14, 20, 24, 26, 34, 39, GND 42 FS2 9 PCICLK_F FS3 10 PCICLK0 FS4 12 PCICLK1 16, 15, 13 PCICLK (4:2) 19, 18 AGPCLK (1:0) 22 48MHz AGPSEL 23 24_48MHz 27 SCLK 28 SDATA 29 AGP_STOP# 30 SDRAM_STOP# 31 PD# 32 CPU_STOP# ...
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... DDR memory. It provides all necessary clock signals for such a system. The ICS9248-199 is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing ...
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... ICS9248-199 Serial Configuration Command Bitmap Bytes 0-3: Are reserved for external clock buffer. Byte4: Functionality and Frequency Select Register (default = ...
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... ICS9248-199 ...
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... ICS9248-199 Byte 8: Byte Count Read Back Register ...
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... ICS9248-199 ...
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... ICS9248-199 Byte 16: Output Divider Control Register ...
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... ICS9248-199 ...
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... ICS9248-199 Byte 21: Slew Rate Control Register ...
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... V DD Logic Inputs X1 & X2 pins To 1st crossing of target frequency From 1st crossing target frequency From target frequency ICS9248-199 +0.5 V MIN TYP MAX 0 0.3 0.8 SS 180 134 39 27 280 600 12 14.318 16 ...
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... ICS9248-199 Electrical Characteristics - CPUCLK (Open Drain 70°C; V =3.3V +/- 5 PARAMETER SYMBOL 1 Output Impedance Z O Output High Voltage V OH2B Output Low Voltage V OL2B I Output Low Current OL2B Fall Time f2B 1 Differential voltage-AC V DIF 1 Differential voltage-DC V DIF 1 Diff Crossover Voltage ...
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... - 1.5 V 100, 133 MHz T 166 MHz 13 ICS9248-199 MIN TYP MAX UNITS 2.6 V 0 1.7 2.0 ns 1.8 2 170 500 ps 265 500 ps MIN TYP MAX UNITS ...
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... ICS9248-199 Electrical Characteristics - IOAPIC 70° 3.3V +/-5 PARAMETER SYMBOL 1 Output Impedance R DSP4B 1 Output Impedance R DSN4B Output High Voltage V OH4 Output Low Voltage V OL4 I Output High Current OH4 I Output Low Current OL4 1 Rise Time t 1 Fall Time Duty Cycle 1 t Jitter, Cycle-to-Cycle ...
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... Index Block Read Operation Controller (Host) T Slave Address D2 WR ACK Beginning Byte = N ACK RT ACK Slave Address D3 RD ACK ACK ICS9248-199 . ICS (Slave/Receiver) starT bit (H) WRite ACK ACK Repeat starT (H) ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK Byte ...
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... ICS9248-199 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS9248- 199 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of ...
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... CPU_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-199. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. ...
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... ICS9248-199 PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-199 used to turn off the PCICLK clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-199 internally. The minimum that the PCICLK clocks are enabled (PCI_STOP# high pulse least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a full high pulse width guaranteed ...
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... SDRAM_STOP asychronous input to the clock synthesizer used to stop SDRAM clocks for low power operation. SDRAM_STOP# is synchronized to complete it's current cycle, by the ICS9248-199. All other clocks will continue to run while the SDRAM clocks are disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...
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... Crystal Notes: 1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248-199 device shown, the outputs Stop Low on the next falling edge after PD# goes low asynchronous input and metastable conditions may exist. This signal is synchronized inside this part. ...
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... Pattern Number ( digit number for parts with ROM code patterns) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists digit numbers) Prefix ICS Standard Device 21 ICS9248-199 In Millimeters In Inches COMMON DIMENSIONS MIN MAX MIN 2.41 2.80 ...