ics9248-146 Integrated Device Technology, ics9248-146 Datasheet - Page 2

• Manufacturer Part Number: ics9248-146
• Description: Single Chip Clock Solution For Sis630s Chipsets.
• Manufacturer: Integrated Device Technology

General Description
The ICS9248-146 is the single chip clock solution for
Desktop/Notebook designs using the SIS 630S style
chipset. It provides all necessary clock signals for such
a system.
Spread spectrum may be enabled through I
programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting
to
board design iterations or costly shielding. The ICS9248-
146
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
stop clock programming and frequency selection.
Pin Configuration
0350B—02/02/04
4, 14, 18, 19, 29,
ICS9248-146
1, 7, 15, 22, 25,
PIN NUMBER
26 33, 34, 36,
37, 38, 40, 41,
13, 12, 11, 10
32, 39, 44
45, 46, 47
17, 16,
35, 43
20
21
23
24
27
28
30
31
48
42
2
3
5
6
8
9
SDRAM_STOP#
CPUCLK (2:0)
PCICLK (4:1)
CPU_STOP#
SDRAM (12,
PCI_STOP#
24_48MHz
PIN NAME
PCICLK_F
SDRAM11
SDRAM10
AGP (1:0)
PCICLK0
SDRAM9
SDRAM8
AGPSEL
SDATA
48MHz
MODE
SCLK
VDDL
REF0
REF1
VDD
GND
PD#
FS3
FS1
FS2
FS0
7:0)
X1
X2
2
C interface allows changing functions,
TYPE
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
AGP frequency select pin.
14.318 MHz reference clock.
Frequency select pin.
14.318 MHz reference clock.
Ground pin for 3V outputs.
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Frequency select pin.
PCI clock output, not affected by PCI_STOP#
Frequency select pin.
PCI clock output.
PCI clock outputs.
AGP outputs defined as 2X PCI. These may not be stopped.
Frequency select pin.
48MHz output clock
Pin 27, 28, 30, & 31 function select pins
0=Desktop 1=Mobile mode
Clock output for super I/O/USB default is 24MHz
Data pin for I
Clock pin of I
Stops all CPUCLKs clocks at logic 0 level, when input is low and
MODE pin is in Mobile mode
SDRAM clock output
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level,
when input is low and MODE pin is in Mobile mode
SDRAM clock output
SDRAM clock output
Stops all SDRAM clocks at logic 0 level, when input is low and
MODE pin is in Mobile mode
Asynchronous active low input pin used to power down the device
into a low power state. The internal clocks are disabled and the
VCO and the crystal are stopped. The latency of the power down will
not be greater than 3ms
SDRAM clock output
SDRAM clock outputs
CPU clock outputs.
Power pin for the CPUCLKs. 2.5V
2
2
C circuitry 5V tolerant
C circuitry 5V tolerant
DESCRIPTION
2
C
2
MODE Pin Power Management Control Input
Power Groups
Analog
VDDA = X1, X2, Core, PLL
VDD48 = 48MHz, 24MHz, fixed PLL
Digital
VDDPCI = PCICLK_F, PCICLK
VDDSDR = SDRAM
VDDAGP=AGP, REF
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