ics9248-99 Integrated Device Technology, ics9248-99 Datasheet - Page 2

• Manufacturer Part Number: ics9248-99
• Description: Frequency Generator & Integrated Buffers For Celeron & Pii/iii
• Manufacturer: Integrated Device Technology

General Description
The ICS9248-99 is the single chip clock solution for Desktop
designs using 810/810/E style chipset. It provides all
necessary clock signals for such a system.
Spread spectrum may be enabled through I
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-
99
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
stop clock programming and frequency selection.
Pin Configuration
0314C—09/18/03
2, 6, 16, 24, 27, 34,
ICS9248-99
5, 9, 13, 20, 26, 30,
31, 32, 33, 35, 36,
19, 18, 17, 15, 14
PIN NUMBER
37, 39, 40, 41
21, 22
44, 45
8, 7
42
10
11
12
23
25
28
29
43
46
47
48
38
1
3
4
CPUCLK [1:0]
SDRAM [8:0]
PCICLK [7:3]
2
VDDLAPIC
PIN NAME
GNDLCPU
VDDLCPU
SEL24_48#
24_48MHz
C interface allows changing functions,
3V66 [1:0]
PCICLK0
PCICLK1
PCICLK2
SDATA
IOAPIC
48MHz
SCLK
REF1
VDD
GND
PD#
FS3
FS0
FS1
FS2
X1
X2
TYPE
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
2
C programming.
14.318 MHz reference clock.
Frequency select pin.
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Ground pin for 3V outputs.
Frequency select pin.
PCI clock output.
Frequency select pin.
PCI clock output.
Frequency select pin.
PCI clock output.
PCI clock outputs.
48MHz output clocks
Select pin for enabling 24MHz or 48MHz
H=24MHz L=48MHz
Clock output for super I/O/USB
Data input for I2C serial input, 5V tolerant input
Clock input of I2C input, 5V tolerant input
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
SDRAM clock outputs
Ground pin for the CPU clocks.
CPU clock outputs.
Power pin for the CPUCLKs. 2.5V
2.5V clock output.
Power pin for the IOAPIC. 2.5V
3.3V clock outputs
2
Power Groups
GNDREF, VDDREF = REF1, X1, X2
GNDPCI , VDDPCI = PCICLK [7:0]
GNDSDR, VDDSDR = SDRAM [8:0]
GNDCOR, VDDCOR = supply for PLL core
GND3V66 , VDD3V66 = 3V66
VDD48 = 48MHz, 24_48MHz,
VDDLAPIC = IOAPIC
GNDLCPU , VDDLCPU = CPUCLK [1:0]
DESCRIPTION