ics9248-81 Integrated Device Technology, ics9248-81 Datasheet - Page 2

• Manufacturer Part Number: ics9248-81
• Description: Frequency Generator & Integrated Buffers
• Manufacturer: Integrated Device Technology

Pin Descriptions
ICS9248 -81
15,28,29,31,32,
Pin number
13, 12, 11, 10
34,35,37,38
3,9,16,22,
27,33,39
40,41,43
25
26
30,36
44
46
6,14
17
18
20
21
2
7
8
19
23
24
42
45
47
48
1
4
5
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
SDRAM_STOP#
CPUCLK [3:1]
PCICLK [4:1]
SDRAM [7:0]
CPU_STOP#
CPU3.3#_2.5
Pin name
SDRAM 12,
PCI-STOP#
SEL24_14#
SDRAM 11
SDRAM 10
VDDLAPIC
PCICLK_F
VDDLCPU
PCICLK 0
VDDSD/C
SDRAM 9
SDRAM 8
VDDSDR
VDDR/X
VDDPCI
SD_SEL
48 MHz
IOAPIC
SDATA
GNDL
REF0
SCLK
REF2
REF1
Mode
GND
PD#
FS1
FS2
SIO
FS0
X1
X2
Type
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Power
Power
Power
0utput
Power
Power
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Isolated 3.3 V power for crystal & reference
3.3V, 14.318 MHz reference clock output.
Function select pin, 1=desk top mode, 0=mobile mode. Latched input.
3.3 V Ground
14.318 MHz crystal input
14.318 MHz crystal output
3.3 V power for the PCI clock outputs
Logic input frequency select bit. Input latched at power-on.
3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#
3.3 V PCI clock outputs, generating timing requirements for Pentium II
Logic input frequency select bit. Input latched at power-on.
3.3 V PCI clock outputs, generating timing requirements for Pentium II
SDRAM clock outputs. Frequency is selected by SD-Sel latched input.
SDRAM clock outputs. Frequency is selected by SD-Sel latched input.
Asynchronous active low input pin used to stop the CPUCLK in low state,
all other clocks will continue to run. The CPUCLK will have a "Turnon" latency
of at least 3 CPU clocks.
SDRAM clock outputs. Frequency is selected by SD-SEL latched input.
Synchronous active low input used to stop the PCICLK in a low state. It will not
effect PCICLK_F or any other outputs.
3.3 V power for SDRAM outputs and core
SDRAM clock outputs. Frequency is selected by SD-Sel latched input.
Asynchronous active low input used to stop the SDRAM in a low state.
It will not effect any other outputs.
SDRAM clock outputs. Frequency is selected by SD-Sel latched input.
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
Data input for I
Clock input of I
This input pin controls the frequency of the SIO. If logic 0 at power on
SIO=14.318 MHz . If logic 1 at power-on SIO=24MHz.
Super I/O output. 24 or 14.318 MHz. Selectable at power-up by SEL24_14MHz
Logic input frequency select bit. Input latched at power-on.
3.3 V 48 MHz clock output, fixed frequency clock typically used with
USB devices
3.3 V power for SDRAM outputs
2.5 V CPU and Host clock outputs
2.5 V power for CPU
3.3V, 14.318 MHz reference clock output.
This pin selects the operating voltage for the CPU. If logic 0 at power on
CPU=3.3 V and if logic 1 at power on CPU=2.5 V operating voltage.
2.5 V Ground for the IOAPIC or CPU
3.3V, 14.318 MHz reference clock output.
This input pin controls the frequency of the SDRAM.
2.5V fixed 14.318 MHz IOAPIC clock outputs
2.5 V power for IOAPIC
Description
2
2
C serial input.
C input