ics9248-39 Integrated Device Technology, ics9248-39 Datasheet
ics9248-39
Related parts for ics9248-39
ics9248-39 Summary of contents
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... Integrated Circuit Systems, Inc. Frequency Generator & Integrated Buffers for PENTIUM/Pro General Description The ICS9248-39 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions. ...
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... ICS9248-39 Pin Descriptions ...
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... ICS9248-39 ...
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... ICS9248-39 Serial Configuration Command Bitmap Byte0: Functionality and Frequency Select Register (default = ± ± ...
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... ICS9248-39 ...
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... ICS9248-39 Byte 4: Reserved Active/Inactive Register (1 = enable disable ...
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... Logic Inputs X1 & X2 pins From target Freq 3.3 V +/-5 2.5 V +/-5% (unless otherwise stated) DDL CONDITIONS pF; Select @ 66.8 MHz pF; Select @ 100 MHz 1 1. ICS9248-39 +0 MIN TYP MAX 0 0.3 0 2.0 -200 -100 146 180 ...
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... ICS9248-39 Electrical Characteristics - CPUCLK 70° 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH2B Output Low Voltage V OL2B Output High Current I OH2B Output Low Current I OL2B 1 Rise Time t r2B 1 Fall Time t f2B 1 Duty Cycle d t2B 1 Skew t sk2B 1 Jitter, Cycle-to-cycle t ...
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... DDL L CONDITIONS ICS9248-39 MIN TYP MAX UNITS 2.4 2.9 V 0.4 0.4 V - 190 500 MIN TYP MAX UNITS 2 2 ...
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... ICS9248-39 Electrical Characteristics - 24MHz, 48MHz, REF(0: 70° 3.3 V +/-5 PARAMETER SYMBOL Output High Voltage V OH5 Output Low Voltage V OL5 Output High Current I OH5 Output Low Current I OL5 1 Rise Time Fall Time Duty Cycle Jitter, One Sigma ...
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... ACK ACK ACK ACK ACK 2 C component. It can read back the data stored in the latches for 2 C interface, the protocol is set to use only "Block-Writes" from the controller. 11 ICS9248- programming. How to Read: ICS (Slave/Receiver) Start Bit Address D3 (H) ACK Byte Count ...
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... CPU_STOP asychronous input to the clock synthesizer used to turn off the CPU clocks for low power operation. CPU_STOP# is synchronized by the ICS9248-39. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is 100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse ...
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... PCI_STOP# Timing Diagram PCI_STOP asynchronous input to the ICS9248-39 used to turn off the PCICLK (0:4) clocks for low power operation. PCI_STOP# is synchronized by the ICS9248-39 internally. The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP# high pulse least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse width guaranteed ...
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... ICS9248-39 Shared Pin Operation - Input/Output Pins The I/O pins designated by (input/output) on the ICS9248- 39 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of ...
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... Optional EMI capacitor should be used on all CPU, SDRAM, and PCI outputs. 3 Optional crystal load capacitors are recommended. Capacitor Values: C1 Crystal load values determined by user C3 : 100pF ceramic All unmarked capacitors are 0.01µF ceramic 0277G—08/04/04 15 ICS9248-39 ...
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... ICS9248-39 TOP VIEW A 2 SEE DETAIL “A” ° 0 Ordering Information ...