ics9lprs535 Integrated Device Technology, ics9lprs535 Datasheet - Page 13

• Manufacturer Part Number: ics9lprs535
• Description: Integrated Circuit Systems, Inc.
• Manufacturer: Integrated Device Technology

1461A—07/28/09
Byte 8 Device ID and Output Enable Register
Byte 9 Output Control Register
Byte 10 Stop Enable Register
Byte 11 iAMT Enable Register
Byte 12 Byte Count Register
Bit
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Note Rev B device default is 0. Rev C device is 1
Pin
Pin
Pin
Pin
Pin
Integrated
Circuit
Systems, Inc.
SRC5_EN Readback
CPU 1 Stop Enable
CPU 2 Stop Enable
CPU 0 Stop Enable
Test Mode Select
PCIF5 STOP EN
WOL_STOP_EN
Test Mode Entry
CPU2_AMT_EN
CPU1_AMT_EN
TME_Readback
REF Strength
PCI-E_GEN2
Device_ID3
Device_ID2
Device_ID1
Device_ID0
IO_VOUT2
IO_VOUT1
IO_VOUT0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
SE1_OE
Name
Name
Name
Name
Name
BC5
BC4
BC3
BC2
BC1
BC0
differentiating between CK505 package options, etc.
Enable 25MHz WLAN clock during M1 or Power Down.
Allows control of PCIF5 with assertion of PCI_STOP#
Allows entry into test mode, ignores FSB/TestMode
Enables control of CPU 2 (ITP)with CPU_STOP#
IO Output Voltage Select (Least Significant Bit)
IO Output Voltage Select (Most Significant Bit)
Allows test select, ignores REF/FSC/TestSel
Table of Device identifier codes, used for
Enables control of CPU 0 with CPU_STOP#
Enables control of CPU1 with CPU_STOP#
Truested Mode Enable (TME) strap status
M1 mode clk enable, only if ITP_EN=1
Determines if PCI-E Gen2 compliant
Sets the REF output drive strength
Readback of SRC5 enable latch
Read Back byte count register,
IO Output Voltage Select
Output enable for SE1
M1 mode clk enable
This bit is sticky 1.
max bytes = 32
Description
Description
Description
Description
Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
13
Type
Type
Type
Type
Type
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
R
R
R
R
R
R
25MHz disabled in
Powerdown or M1
Normal operation
normal operation
CPU/PCI Stop
Free Running
Free Running
Free Running
Outputs HI-Z
Free running
1X (2Loads)
non-Gen2
Disabled
Enabled
Disable
Disable
See Table 3: V_IO Selection
TBD
TBD
TBD
TBD
TBD
Byte count is 13 decimal.
0
0
0
0
0
-
-
-
-
-
-
See Device ID Table
(Default is 0.8V)
ICS9LPRS535
25MHz enabled in
Powerdown or M1
Outputs = REF/N
no overclocking
SRC5 Enabled
2X (3 Loads)
PCI_STOP#
PCI-E Gen2
Stops with
Test mode
Stoppable
Stoppable
Compliant
Stoppable
assertion
Enabled
Enable
Enable
TBD
TBD
TBD
TBD
TBD
1
1
1
1
1
Datasheet
-
-
-
-
-
-
Default
Default
Default
Default
Default
NOTE
Latch
0
1
1
0
0
0
1
0
0
0
1
0
0
1
0
1
0
0
0
0
0
1
1
0
0
1
0
1
1
1
0
0
0
0
1
1
0
1