ics9lprs535 Integrated Device Technology, ics9lprs535 Datasheet - Page 17

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ics9lprs535

Manufacturer Part Number
ics9lprs535
Description
Integrated Circuit Systems, Inc.
Manufacturer
Integrated Device Technology
Datasheet
1461A—07/28/09
Revision History
Rev.
0.1
0.2
0.3
0.4
0.5
0.6
0.7
A
Integrated
Circuit
Systems, Inc.
Issue Date Description
3/10/2008
4/23/2008
7/10/2008
7/13/2009
7/21/2009
7/28/2009
5/7/2008
7/7/2008
1. Intial release
1. Updated SMBus, front page, block diagram and deleted page 5
1. Corrected typo in CPU power management table. Wrong column heading
2. Corrected typo in PD# Power Management Table SE1 should be low when
B11b5 = 0
3. Corrected Byte 5 bit 0 to be NA when set to 0. SRC1 is not present.
4. Byte 6, bit 6 restored. CR_F# is present and can control SRC8
1. Corrected Power management table to remove the stop mode drive bits, which
do not exist in this device.
2. Updated Differential clock period table.
1. Updated pin names to reflect LPR output type. Pin descriptions updated too.
2. SMBus updated to indicate PCIe Gen2 status
1. Removed references to CR# inputs that do not exist in this part.
2. Clarified functionality of Byte 11, bit 5.
1. Lowered Idd values to reflect performance of the device.
1. Moved to final
2. Added "Wake-on LAN Default" parameter to ordering info table.
17
ICS9LPRS535
Datasheet
1, 4, 12-13
Various
Various
Various
Various
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