ics9lprs535 Integrated Device Technology, ics9lprs535 Datasheet - Page 6

• Manufacturer Part Number: ics9lprs535
• Description: Integrated Circuit Systems, Inc.
• Manufacturer: Integrated Device Technology

1461A—07/28/09
NOTES on Input/Supply/Common Output DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
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Electrical Characteristics - Input/Supply/Common Output DC Parameters
Spread Spectrum Modulation Frequency
Low Threshold Input- FSC = '1' Voltage
Maximum SMBus Operating Frequency
Signal is required to be monotonic in this region.
input leakage current does not include inputs with pull-up or pull-down resistors
3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if selected.
Intentionally blank
Maximum VIH is not to exceed VDD
Operation under these conditions is neither implied, nor guaranteed.
Frequency Select pins which have tri-level input
PCI3/CFG0 is optional
Human Body Model
If present. Not all parts have this feature.
Low Threshold Input- FSA,FSB = '1'
Low Threshold Input- High Voltage
Low Threshold Input-Low Voltage
Current sinking at V
Operating Supply Current
Ambient Operating Temp
Low-level Output Voltage
Input Leakage Current
Input Leakage Current
Clock/Data Rise Time
Clock/Data Fall Time
Output High Voltage
Output Low Voltage
iAMT Mode Current
Powerdown Current
Input High Voltage
Input Capacitance
Input Low Voltage
Integrated
Circuit
Systems, Inc.
Input Frequency
Clk Stabilization
Supply Voltage
Supply Voltage
Pin Inductance
Tdrive_CR_off
Tdrive_CR_on
SMBus Voltage
PARAMETER
SCLK/SDATA
SCLK/SDATA
Tdrive_CPU
Trise_SE
Tfall_SE
Voltage
OLSMB
= 0.4 V
VDDxxx_IO
V
V
SYMBOL
V
Tambient
T
I
VDDxxx
T
I
IH_FS_TEST
IH_FS_FSAB
I
DDiAMT3.3
I
IH_FS_FSC
DDiAMTIO
T
V
F
I
I
I
DRCROFF
f
V
V
V
DDOP3.3
DDPD3.3
I
DDOPIO
DDPDIO
T
DRCRON
PULLUP
V
C
T
T
T
SSMOD
V
T
C
INRES
DRSRC
V
OLSMB
SMBUS
L
C
OHSE
STAB
IL_FS
OLSE
FALL
IHSE
I
RISE
RI2C
FI2C
ILSE
F
OUT
IN
INX
pin
DD
IN
i
Fall/rise time of all 3.3V control inputs from 20-80%
From VDD Power-Up or de-assertion of PD to 1st
Inputs with pull up or pull down resistors
Low-Voltage Differential I/O Supply
Full Active, C
Single-ended outputs, I
Full Active, C
Single-ended outputs, I
Output stop after CR deasserted
Power down mode, 3.3V Rail
Output run after CR asserted
Power down mode, IO Rail
PCI_STOP# de-assertion
Single-ended 3.3V inputs
Single-ended 3.3V inputs
CPU output enable after
Output pin capacitance
Triangular Modulation
V
V
M1 mode, 3.3V Rail
(Min VIH + 0.15) to
(Max VIL - 0.15) to
IN
IN
M1 Mode, IO Rail
6
(Min VIH + 0.15)
(Max VIL - 0.15)
Supply Voltage
CONDITIONS
SMB Data Pin
= V
= V
X1 & X2 pins
Logic Inputs
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
3.3 V +/-5%
V
@ I
L
DD
DD ,
DD ,
L
= Full load; Idd 3.3V
clock
= Full load; IDD IO
= 3.3 V
PULLUP
-
V
V
IN
IN
= GND
= GND
OH
OL
= -1mA
= 1 mA
V
V
0.9975
3.135
SS
SS
-200
MIN
0.7
0.7
2.4
1.5
2.7
30
-5
0
2
2
ICS9LPRS535
4
- 0.3
- 0.3
VDD + 0.3
VDD+0.3
V
DD
3.465
3.465
MAX
1000
0.35
200
125
400
300
100
0.8
1.5
0.4
0.1
1.8
5.5
0.4
70
50
40
10
15
10
10
10
33
5
5
7
5
6
6
0
+ 0.3
Datasheet
UNITS Notes
MHz
kHz
kHz
mA
mA
mA
mA
mA
mA
mA
uA
uA
nH
ms
°C
pF
pF
pF
ns
us
ns
ns
ns
ns
ns
V
V
V
V
V
V
V
V
V
V
V
V
10
10
10
3
3
8
8
2
1
1