ics1523 Integrated Device Technology, ics1523 Datasheet - Page 12

• Manufacturer Part Number: ics1523
• Description: Video Clock Synthesizer With I?c Programmable Delay
• Manufacturer: Integrated Device Technology

MDS ICS1523 Z
Section 11 Programming
11.1 Industry-Standard I
Note:
Write Procedure for Single Re gis ter
Re ad Proce dure for Single Re gis te r
Write Procedure for M ultiple Regis te rs (Note 1)
Re ad Proce dure for M ultiple Re gis te rs (Note 1)
All values are sent with the most-significant bit (MSB) first and least-significant bit (LSB) last.
W
Legend
A
A
S 0 1 0 0 1 1 X 0 A
S 0 1 0 0 1 1 X 0 A
S 0 1 0 0 1 1 X 0 A
S 0 1 0 0 1 1 X 0 A
R
S
X
MSB
MSB
MSB
MSB
= Write = 0
= Start (SDA goes low when SCL was high, then SCL goes low too)
= ACK = Acknowledge = 0
= ACK = No Acknowledge = 1
= Bit value that equals logic state of SBADR pin.
Bus Master drives signal to ICS1523
Device address
Device address
Device address
Device address
= Read = 1
= (Dashed Line) Multiple transactions
Figure 11-1 ICS1523 Data Format for I
•
•
1 - Lower nibble of the I
or read from the ICS1523.
2 - Upper nibble of the I
re-address the ICS1523. The software:
– Must NOT just index 0 and then do all the I/O as one-byte transactions.
– Must break the transactions into at least two separate bus transactions:
(1) 00 to 08 (2) 10 to 12
LSB
LSB
LSB
LSB
Integrated Device Technology, Inc.
Register Index
Register Index
Register Index
Register Index
2
2
C Serial Bus: Data Format
2
C register automatically increments after each successive data byte is written to
C register does not automatically increment, and the software must explicitly
A
A S 0 1 0 0 1 1 X 1 A
A
A S 0 1 0 0 1 1 X 1 A
ICS1523 (Slave Device) drives signal to Bus Master
MSB
Repeat START
MSB
Repeat START
Device address
Device address
Data
Data
2
C 2-Wire Serial Bus
12
Tech Support: www.idt.com/go/clockhelp
Video Clock Synthesizer with I
LSB
LSB
A
A
Stop
Data
Data
Data
A
A
A
NO Acknow ledge
Stop
2
C Programmable Delay
NO Acknow ledge
Data
Revision 052407
ICS1523
A
A
Stop
Stop