ics1523 Integrated Device Technology, ics1523 Datasheet - Page 7

• Manufacturer Part Number: ics1523
• Description: Video Clock Synthesizer With I?c Programmable Delay
• Manufacturer: Integrated Device Technology

MDS ICS1523 Z
4.1 Register Set Summary (continued)
0x6
0x7
0x8
0x10
0x11
0x12
Index
Reg.
Chip Rev Read
Osc_Div
Chip Ver
Rd_Reg
Enables
Output
Name
Reset
R / W
R / W
Write
Read
Read
Access
Integrated Device Technology, Inc.
Bit Name
PLL_Lock
Reserved
Reserved
Chip Rev
Osc_Div
Chip Ver
OE_Pck
OE_Tck
Ck2_Inv
Out_Scl
OE_P2
OE_T2
OE_F
In-Sel
DPA
PLL
0-6
Bit #
6-7
0-6
0-3
4-7
0-7
0-7
2-7
0
1
2
3
4
5
7
0
1
Reset
Value
N/A
N/A
17
01
0
0
0
0
0
0
0
0
1
x
0
x
7
Output Enable for PECL CLK (Pins 20, 21)
0=High Z, 1=Enabled
Output Enable for STTL_3 CLK (Pin 17)
0=High Z, 1=Enabled
Output Enable for PECL CLK/2 (Pins 22, 23)
0=High Z, 1=Enabled
Output Enable for STTL_3 CLK/2 (Pin 16)
0=High Z, 1=Enabled)
Output Enable for STTL_3 FUNC Output (Pin15)
0=High Z, 1=Enabled
CLK/2 Invert (0=Not Inverted, 1= Inverted)
CLK Scaler (pin 17)
Bit 7, 6 = (00 = ÷ 1, 01 = ÷ 2, 10 = ÷ 4, 11 = ÷ 8)
See
Osc Divider modulus
See
Input Select
0=HSYNC Input, 1=Osc Divider
Writing xAh resets DPA and loads working 0x5
Writing 5xh resets PLL and loads working 0x1- 0x3
Chip Version 23 Dec (17h) as in 1523
Reserved
PLL Lock Status
0=Unlocked, 1=Locked
Reserved
Initial value 01h. Value Increments with each all-layer change.
Tech Support: www.idt.com/go/clockhelp
Video Clock Synthesizer with I
Section 5, “Register Set Details”
Section 6, “OSC Divider and REF”
Description
2
C Programmable Delay
Revision 052407
ICS1523
Notes