ics1523 Integrated Device Technology, ics1523 Datasheet - Page 17
ics1523
Manufacturer Part Number
ics1523
Description
Video Clock Synthesizer With I?c Programmable Delay
Manufacturer
Integrated Device Technology
Datasheet
1.ICS1523.pdf
(21 pages)
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MDS ICS1523 Z
12.3 HSYNC to REF Timing
12.4 CLK/2 Timing for Odd and Even Feedback Divider
For simplicity, the waveforms drawn show only the identical PECL CLK/2+ and the SSTL_3 CLK/2 signals. CLK/2-
is the compliment of the CLK/2+ signal.
Note that regardless of the CLK\2 phase at the assertion of FUNC, the clocks always have the same phase at the
fall of FUNC, regardless of 0x2
Figure 12-4 HSYNC to REF Timing Diagram
Table 12-4 HSYNC to REF Timing Diagram
Figure 12-5 CLK/2: Even versus Odd
Symbol Parameter
T
T
0
1
Even - Reg2:0=0
Integrated Device Technology, Inc.
HSYNC Low to REF Delay
HSYNC High to REF Delay
Odd - Reg2:0=1
Reg0:2 = 1
Reg0:2 = 0
FUNC
CLK/2
CLK/2
HSYNC
HSYNC
REF
REF
17
Tech Support: www.idt.com/go/clockhelp
Video Clock Synthesizer with I
t
t1
0
Minimum
3.5
6
Typical
t1
t0
7.5
4.3
2
C Programmable Delay
Maximum
8.5
6
Revision 052407
ICS1523
Units
ns
ns