vsc880 Vitesse Semiconductor Corp, vsc880 Datasheet - Page 16

• Manufacturer Part Number: vsc880
• Description: High Performance 16x16 Serial Crosspoint Switch Semiconductor Corporation
• Manufacturer: Vitesse Semiconductor Corp

High Performance 16x16
Serial Crosspoint Switch
Page 16
2.4 Arbitration
requests come into the switch chip on each word clock, and the arbitration process takes two word clock cycles.
Arbitration is round-robin with the last connection to an output getting the lowest priority for that output. For
multicast, if BRK is LOW, arbitration will only be performed on the requested connections that are not currently
granted. If a port is in the out of synch state, any connection request to this port will be always granted.
reconfiguration time is delayed D word clocks after the time arbitration results are determined. This allows the user
logic to receive arbitration results ahead of time so the port cards do not have to block data while waiting for these
results. If the CRQ word is inserted into the current data packet D words before the end of the packet, arbitration
results will be known at the port card just as the first word of the next data packet is ready for transmission, thus
improving bandwidth utilization. The number D is selected based on the round trip delay from the time the port
submits a CRQ until an ACK is received and the FIFO is ready to send a data word. This value of D is a system wide
value and must be used by all port cards. D should be set to a maximum value equal to the round trip delay (typically
8 word clocks).
arbitration during two word clock cycles. The first level determines which of the requested outputs are available and
holds these outputs. The second level chooses one winner from the available outputs then releases the rest. Because
outputs can be blocked during the first level of arbitration, all Muti Queue CRQ commands are held at the switch chip
and continue to request outputs until a connection is granted or a header word is detected. If a header word is detected
at the transceiver, a repeated sequence of CRQ words is sent to the switch until a connection is granted. The port
number of the granted output is returned to the port card using the two overhead bits (see VSC870 data sheet).
Example 1:
In Packet Mode, if multiple inputs request a connection to the same output, arbitration is performed. Connection
For Multi Queue connection requests from the transceiver (ARB = 1), the switch chip performs two levels of
In order to improve bandwidth utilization, a system wide mode of operation can be used where the switch matrix
11
BB
BB
BB
00
00
00
BB
11
Header
Header
IDLEs
CRQ
CRQ
D0
D1
DN
CRQ
D0
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Figure 7: Packet Transmission Format from Transceiver
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
VITESSE
Start of Packet
End of Packet
Zero or more IDLEs
SEMICONDUCTOR CORPORATION
Internet: www.vitesse.com
Example 2:
11
BB
00
BB
BB
11
BB
00
00
Header
Header
IDLEs
CRQ
CRQ
CRQ
D0
D(N-D)
DN
D0
Start of Packet
D words before EOP
End of Packet
Zero or more IDLEs
Data Sheet
VSC880
G52191-0, Rev 4.2
01/05/01