vsc880 Vitesse Semiconductor Corp, vsc880 Datasheet - Page 6

• Manufacturer Part Number: vsc880
• Description: High Performance 16x16 Serial Crosspoint Switch Semiconductor Corporation
• Manufacturer: Vitesse Semiconductor Corp

High Performance 16x16
Serial Crosspoint Switch
Page 6
1.1.6 Link Error Detection
IDLE words. If a link error is detected, a bit in the LERR register is set HIGH for that particular channel (see section
1.4). After every 8 link errors, a bit in the TERR register is set HIGH. If the DRU goes out of range, a bit in the DERR
register is set HIGH. If the last word in the cell period is an IDLE word and it does not have bits B[1:0] set HIGH to
designate a cell clock, a bit in the CERR register will be set HIGH. If an error bit is set in any of these registers, the
INT signal can be programmed to go LOW and/or the link can be programmed to automatically start link
initialization depending on the value loaded into the Interrupt Control Register (see section 1.4). These error register
bits will be cleared if the link is reinitialized, or the registers are read. If the signal RESYNEN is set HIGH, link
initialization will begin immediately upon the detection of any of these errors. If the switch is used without IDLE
words, the user is responsible for detecting parity error conditions and restarting the link initialization process.
1.2 Data Encoding Format
Depending on the mode that the switch is used in, different word types are recognized by the switch. In both the
Packet and Cell Modes, the switch processes both data words and command words. They have the same format in
both modes and will be described in following section. The format for the connection request words and header
words are described later in the Packet Mode section.
1.2.1 Data Word Format on the Serial Data Lines
bits are added by the transceiver or switch chip to designate a data word to the receiving switch chip or transceiver.
The serial data is transmitted with the MSB first.
1.2.2 Command Word Format on the Serial Data Lines
overhead bits are added by the transceiver or switch to designate a command word (00) to the receiving switch chip or
transceiver. The serial data is transmitted with the MSB first. In Packet Mode, the IDLE word from the switch always
returns the current output connections for the port.
To provide self-routing and cell synchronization, the transceiver and switch require special word formats.
The data word format as seen at the serial output of the transceiver or switch chip is shown below. Two overhead
Where:
B[1:0]If Packet Mode,
D[31:0]32 bit data payload
The command word format as seen at the serial output of the transceiver or switch chip is shown below. Two
33 32
B B
1 0
There are four types of link errors that can be flagged on the receive serial links. Link errors are detected using
If Cell Mode,
31 30 29 28
D D D D
31 30 29 28
10=Flow control channel,
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27 26 25 24
D D D D
27 26 25 24
11=Acknowledge from switch chip or header word to switch chip
01, 10, 11 = data
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SEMICONDUCTOR CORPORATION
01=Flow control channel,
23 22 21 20
D D D D
23 22 21 20
--------------- Data Payload ----------------
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19 18 17 16
D D D D
19 18 17 16
15 14 13 12
D D D D
15 14 13 12
11 10 09 08
D D D D
11 10 09 08
07 06 05 04
D D D D
07 06 05 04
03 02 01 00
D D D D
03 02 01 00
Data Sheet
VSC880
G52191-0, Rev 4.2
01/05/01