vsc880 Vitesse Semiconductor Corp, vsc880 Datasheet - Page 3

• Manufacturer Part Number: vsc880
• Description: High Performance 16x16 Serial Crosspoint Switch Semiconductor Corporation
• Manufacturer: Vitesse Semiconductor Corp

G52191-0, Rev 4.2
01/05/01
Data Sheet
VSC880
RESYNEN
SCANOUT
FACLPBK
BSTLPBK
BSTPASS
TCLKEN
REFCLK
TESTEN
SCANIN
BSTRST
CMODE
BSTEN
RESET
WCLK
CCLK
MEN
INT
Pin
Built-in Self Test Enable
Built-in Self Test Reset
Built-in Self Test Loop
Built-in Self Test Pass
Facility Loop Back
Test Clock Enable
Scan Test Enable
Reference Clock
Resynch Enable
Scan Data Out
Scan Data In
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Word Clock
Cell Mode
Cell Clock
Reserved
Interrupt
Name
Reset
Back
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
VITESSE
SEMICONDUCTOR CORPORATION
I/O
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O
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Internet: www.vitesse.com
62.5Mb/s
62.5Mb/s
62.5MHz
62.5MHz
62.5MHz
<1MHz
<1MHz
<1MHz
<1MHz
<1MHz
<1MHz
<1MHz
<1MHz
<1MHz
<1MHz
<1MHz
<1MHz
Freq
Type
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
If RESYNEN is HIGH, all links that have a link error
condition will be reinitialized. This will override the internal
control register settings.
If INT is LOW, a receive error has occurred in one of the
links that has it’s output enable (OE) bit set HIGH and
interrupt control register bit set HIGH.
This signal is reserved for future use and should be set LOW
during normal operation.
If this signal is set HIGH, all serial inputs are looped back to
their serial outputs. This will override the internal control
register setting.
CMODE is set HIGH for Cell Mode operation.
This signal is used in ATE testing to measure propagation
delay. It is also used in ATE testing of the BIST logic. Set to
logic LOW in normal operation.
The input signal for measuring propagation delay on the
ATE tester.
The output signal for measuring propagation delay on the
ATE tester. When TESTEN is set LOW, the longer delay
path is enabled.
This is the word clock output.
This is the reference clock and the source of the system wide
word clock period.
This input is set HIGH in test mode, so that the CMU is
bypassed and the REFCLK becomes the bit clock. This
signal is for ATE test only. Set LOW in normal operation.
This is the source of the system wide cell clock. It is
internally synchronized to the REFCLK. In Packet mode, set
this signal HIGH to enable external switch configuration for
BIST.
Global chip reset (active LOW)
When BSTLPBK is set HIGH and TESTEN is LOW, all
serial data output signals are looped back to their serial data
inputs. If BSTLPBK is set HIGH and TESTEN is HIGH,
only ports 0-7 are placed in loopback.
When BSTEN is HIGH, at-speed built-in self testing is
enabled.
The BSTRST signal is set HIGH to reset the PRBS
generator and comparator.
The BSTPASS signal is HIGH if BTSEN is HIGH and the
PRBS comparator detects the correct pattern in built-in self
test mode.
Description
High Performance 16x16
Serial Crosspoint Switch
Page 3