vsc880 Vitesse Semiconductor Corp, vsc880 Datasheet - Page 9

• Manufacturer Part Number: vsc880
• Description: High Performance 16x16 Serial Crosspoint Switch Semiconductor Corporation
• Manufacturer: Vitesse Semiconductor Corp

G52191-0, Rev 4.2
01/05/01
Data Sheet
VSC880
ADDR[5:0]
X 1 0 1 1 1
X 1 0 1 0 0
X 1 0 1 0 1
X 1 0 1 1 0
X 1 1 0 0 0
X 1 1 0 0 1
X 1 1 0 1 0
X 1 1 0 1 1
Where:
CE Cell clock errorRCE
DE DRU error RDE
TE Threshold errorRTE
LE Link error RLE
BIST
CDEL[3:0]
CERR[15:0]Cell clock error register, bit 0 is channel 0 etc, Cleared on read
DERR[15:0]DRU error register, bit 0 is channel 0 etc. Cleared on read
TERR[15:0]Threshold error register, bit 0 is channel 0 etc. Cleared on read
LERR[15:0]Link error register, bit 0 is channel 0 etc, Cleared on read
CN[3:0]Switch configuration data. N is the output port number, [3:0] is the input port connected. Default = 0xF.
SN[3:0]Output status data. N is the output port number, SN[3:2] = 00 for normal operation.
0 1 0 0 1 1
1 0 1 1 0 0
1 0 1 1 0 1
1 0 1 1 1 0
1 0 1 1 1 1
1 1 0 0 0 0
1 1 0 0 0 1
1 1 0 0 1 0
1 1 0 0 1 1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
Set this bit HIGH to test the BIST circuitry
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Cell clock delay
7
Tel: (800) VITESSE • FAX: [phone] • Email: [e-mail]
6
VITESSE
C7[3:0]
S0[3:0]
S1[3:0]
S2[3:0]
S3[3:0]
S4[3:0]
S5[3:0]
S6[3:0]
S7[3:0]
SEMICONDUCTOR CORPORATION
Resynch on cell errorICE
Resynch on DRU errorIDE
Resynch on thresh errorITE
Resynch on link errorILE
CDATA[7:0] Bit Position
5
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LPBK[15:8]
LPBK[7:0]
4
RSY[15:8]
RSY[7:0]
OE[15:8]
FI[15:8]
OE[7:0]
FI[7:0]
3
01 for out of synch
10 for word synch in progress
11 for cell synch in progress
SN[1] = Output busy in packet mode
SN[0] = Connection valid in packet mode
2
C15[3:0]
S10[3:0]
S11[3:0]
S12[3:0]
S13[3:0]
S14[3:0]
S15[3:0]
S8[3:0]
S9[3:0]
1
Interrupt on cell error
Interrupt on DRU error
Interrupt on threshold error
Interrupt on link error
0
High Performance 16x16
Serial Crosspoint Switch
Output7/Output15 Config
Output0/Output8 Status
Output1/Output9 Status
Output2/Output10 Status
Output3/Output11 Status
Output4/Output12 Status
Output5/Output13 Status
Output6/Output14 Status
Output7/Output15 Status
Force IDLEs LSB
Force IDLEs MSB
Resynch LSB
Resynch MSB
Output Enable LSB
Output Enable MSB
Loopback LSB
Loopback MSB
Page 9