w83193r-04 Winbond Electronics Corp America, w83193r-04 Datasheet
w83193r-04
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w83193r-04 Summary of contents
Page 1
... DD < 250 pS skew among CPU and SDRAM clocks. < 250 pS skew among PCI clocks. Smooth frequency switch with selections from 50 MHz to 83.3 MHz CPU. (W83193R-04) Smooth frequency switch with selections from 50 MHz to 112 MHz CPU. (W83193R-04A 2-Wire serial interface and I Spread spectrum function to reduce EMI. ...
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... PCICLK0/*FS2 PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDq3 PCICLK5/PCI_STOP# SDRAM11 SDRAM10 Vddq3 SDRAM 9 SDRAM 8 SDATA SDCLK 3.0 BLOCK DIAGRAM Xin Xout FS(0:2)* MODE* CPU3.3#_2.5* CPU_STOP# PCI_STOP# SDATA SCLK Preliminary W83193R-02/-04/-04A VDD Vss 4 Xin 45 Xout Vss 40 10 ...
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... IOAPIC SDRAM [ 0:11] 17, 18, 20, 21, 28, 29, 31, 32, 34, 35, 37, 38 PCICLK_F/ *FS1 PCICLK 0 / *FS2 PCICLK [ 1:4 ] 10, 11, 12, 13 PCICLK5/ PCI_STOP# Preliminary W83193R-02/-04/-04A PIN I Crystal input with internal loading capacitors and feedback resistors. 5 OUT Crystal output at 14.318 MHz nominally. PIN I/O OUT Low skew (< 250 pS) clock outputs for host frequencies such as CPU, Chipset and Cache ...
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... V q2b 14, 19, 30 16, 22, 27, 33, SS 39, 45 Preliminary W83193R-02/-04/-04A I/O 2 I/O Serial data 2-wire control interface 2 IN Serial clock 2-wire control interface I/O I/O Internal 250k pull-up. Latched input for CPU3.3#_2.5 at initial power up. Reference clock during normal operation. ...
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... FREQUENCY SELECTION W83193R-02/-04 Frequency Table FS2 FS1 FS0 W83193R-04A Frequency Table FS2 FS1 FS0 7.0 CPU 3.3#_2.5 BUFFER SELECTION CPU 3 ...
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... The W83193R-02/-04/-04A may be disabled in the low state according to the following table in order to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop. The CPU and PCI clocks transform between running and stop by waiting for one positive edge on PCICLK_F followed by negative edge on the clock of interest, after which high levels of the output are either enabled or disabled ...
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... FUNCTION TABLE FUNCTION DESCRIPTION TRI-STATE NORMAL See table Preliminary W83193R-02/-04/-04A DESCRIPTION - 0 = 1.5% Spread Spectrum Modulation 1 = 0.5% Spread Spectrum Modulation - SSEL2 (Frequency table selection by software via I - SSEL1 (Frequency table selection by software via I - SSEL0 (Frequency table selection by software via Selection by hardware ...
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... Register 3: SDRAM Clock Register (1 = Enable Stopped) BIT @POWERUP PIN Preliminary W83193R-02/-04/-04A - Reserved - Reserved - Reserved - Reserved 40 CPUCLK3 (Active/ Inactive) 41 CPUCLK2 (Active/ Inactive) 43 CPUCLK1 (Active/ Inactive) 44 CPUCLK0 (Active/ Inactive) - Reserved 7 PCICLK_F (Active/ Inactive) 15 ...
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... Register 6: Reserved Register BIT @POWERUP Preliminary W83193R-02/-04/-04A PIN - Reserved - Reserved - Reserved - Reserved 17 SDRAM11 (Active/ Inactive) 18 SDRAM10 (Active/ Inactive) 20 SDRAM9 (Active/ Inactive) 21 SDRAM8 (Active/ Inactive) PIN - Reserved - Reserved - Reserved 47 IOAPIC (Active/ Inactive) ...
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... PCI), (SDRAM-SDRAM) CPU/SDRAM Cycle to Cycle Jitter CPU/SDRAM Absolute Jitter Jitter Spectrum 20 dB Bandwidth from Center Output Rise (0.4V 2.0V) & Fall (2.0V 0.4V) Time Overshoot/Undershoot Beyond Power Rails Ring Back Exclusion Preliminary W83193R-02/-04/-04A SYMBOL q2b = 2.375V~2. + MIN. TYP. MAX. ...
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... Buffer Characteristics 9.4.1 Type 1 Buffer for CPU (0:3) PARAMETER Pull-up Current Min. Pull-up Current Max. Pull-down Current Min. Pull-down Current Max. Rise/Fall Time Min. Between 0.4V and 2.0V Rise/Fall Time Max. T Between 0.4V and 2.0V Preliminary W83193R-02/-04/-04A q2b = 2.375V~2. + SYM. MIN. TYP. MAX ...
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... Between 0.8V and 2.0V 9.4.4 Type 4 Buffer for REF0 and SDRAM (0:11) PARAMETER Pull-up Current Min. Pull-up Current Max. Pull-down Current Min. Pull-down Current Max. Rise/Fall Time Min. Between 0.8V and 2.0V Rise/Fall Time Max. T Between 0.8V and 2.0V Preliminary W83193R-02/-04/-04A SYMBOL MIN. TYP. MAX. I (min.) OH (max (min.) OL (max ...
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... CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume output with full pulse width. In this case, CPU "clocks on latency" is less than 2 CPU clocks and "clocks off latency" is less then 2 CPU clocks. Preliminary W83193R-02/-04/-04A MIN. TYP. ...
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... Each of these pins are a large pull-up resistor (250 K 1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these dual function pins. Under these conditions, an external 10 K Preliminary W83193R-02/-04/-04A 1 2 reaches 2.5V, the logic level that is present on these DD 2 ...
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... If optional EMI reducing capacitor are needed, they should be placed as close to the series terminating resistor as possible and after the series terminating resistor. These capacitor has typical values ranging from 4 pF. Device Pin V Pad DD Device Pin Preliminary W83193R-02/-04/-04A V DD Series 10 K Terminating Resistor 10 K Ground Programming Header ...
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... Use of Ferrite Bead (FB) are recommended to further reduce the power supply noise. 5. The power supply race to the V resistance is negligible. FB1 Plane DD (3.3V) C1 C31 C32 C33 C34 Preliminary W83193R-02/-04/-04A pin and the ground via. DD pins must be thick enough so that voltage drops across the trace ...
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... W83193R-02/-04 14.0 HOW TO READ THE TOP MARKING W83193R-02 28051234 814GBB 1st line: Winbond logo and the type number: W83193R-02/-04 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 814: packages made in '98, week 14 G: assembly house ID ...
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... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. Preliminary W83193R-02/-04/-04A Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. ...