w83193r-04 Winbond Electronics Corp America, w83193r-04 Datasheet - Page 14

• Manufacturer Part Number: w83193r-04
• Description: 83.3 Mhz 3-dimm Clock
• Manufacturer: Winbond Electronics Corp America

10.2 PCI_STOP# Timing Diagram (synchronous)
For synchronous Chipset, PCI_STOP# pin is a synchronous active low ” input pin used to stop the
PCICLK [0:5] for low power operation. This pin is asserted synchronously by the external control logic
at the rising edge of free running PCI clock(PCICLK_F). All other clocks will continue to run while the
PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output with
full pulse width. In this case, PCI clocks on latency “ is less than 1 PCI clocks and clocks off latency”
is less then 1 PCI clocks.
11.0 OPERATION OF DUAL FUCTION PINS
Pins 2, 7, 8, 25, and 26 are dual function pins and are used for selecting different functions in this
device (see Pin description). During power up, these pins are in input mode (see Figure 1), therefore,
and are considered input select pins. When V
pins are latched into their appropriate internal registers. Once the correct information are properly
latched, these pins will change into output pins and will be pulled low by default. At the end of the
power up timer (within 3 mS) outputs starts to toggle at the specified frequency.
Each of these pins are a large pull-up resistor (250 K
1, but the internal pull-up resistor may be too large when long traces or heavy load appear on these
dual function pins. Under these conditions, an external 10 K
PCI_STOP#
PCICLK[0:5]
PCICLK_F
CPUCLK
(Internal)
(Internal)
PCICLK
#2 REF0/CPU3.3#_2.5
#7 PCICLK_F/FS1
#8 PCICLK0/FS2
#25 24/MODE
#26 48/FS0
All other clocks
Output
tri-state
Output
tri-state
1
Input
Preliminary W83193R-02/-04/-04A
2.5V
DD
2
- 14 -
reaches 2.5V, the logic level that is present on these
Output
pull-low
Output
pull-low
Within 3ms
@3.3V) inside. The default state will be logic
Output
1
resistor is recommended to be
2
Vdd