lmk04000b National Semiconductor Corporation, lmk04000b Datasheet - Page 20

• Manufacturer Part Number: lmk04000b
• Description: Low-noise Clock Jitter Cleaner With Cascaded Plls
• Manufacturer: National Semiconductor Corporation

www.national.com
Note 8: Load conditions for output clocks: LVPECL: 50 Ω to V
Note 9: Additional test conditions for I
Note 10: CLKin0 and CLKin1 maximum of 400 MHz is guaranteed by characterization, production tested at 200 MHz.
Note 11: In order to meet the jitter performance listed in the subsequent sections of this data sheet, the minimum recommended slew rate for all input clocks is
0.5 V/ns. This is especially true for single-ended clocks. Phase noise performance will begin to degrade as the clock input slew rate is reduced. However, the
device will function at slew rates down to the minimum listed. When compared to single-ended clocks, differential clocks (LVDS, LVPECL) will be less susceptible
to degradation in phase noise performance at lower slew rates due to their common mode noise rejection. However, it is also recommended to use the highest
possible slew rate for differential clocks to achieve optimal phase noise performance at the device outputs.
Note 12: This parameter is programmable
Note 13: F
Note 14: The EN_PLL2_REF2X bit (Register 13) enables/disables a frequency doubler mode for the PLL2 OSCin path.
Note 15: See Application Section discussion of Crystal Power Dissipation.
Note 16: A specification in modeling PLL in-band phase noise is the 1/f flicker noise, L
dB/decade slope. PN10kHz is normalized to a 10 kHz offset and a 1 GHz carrier frequency. PN10kHz = L
(f) is the single side band phase noise of only the flicker noise's contribution to total noise, L(f). To measure L
slope close to the carrier. A high compare frequency and a clean crystal are important to isolating this noise source from the total phase noise, L(f). L
can be masked by the reference oscillator performance if a low power or noisy source is used. The total PLL inband phase noise performance is the sum of
L
Note 17: A specification modeling PLL in-band phase noise. The normalized phase noise contribution of the PLL, L
(f)-20log(N)-10log(f
frequency of the synthesizer. L
Note 18: Maximum Allowable Temperature Drift for Continuous Lock is how far the temperature can drift in either direction from the value it was at the time that
the R0 register was last programmed, and still have the part stay in lock. The action of programming the R0 register, even to the same value, activates a frequency
calibration routine. This implies the part will work over the entire frequency range, but if the temperature drifts more than the maximum allowable drift for continuous
lock, then it will be necessary to reload the R0 register to ensure it stays in lock. Regardless of what temperature the part was initially programmed at, the
temperature can never drift outside the frequency range of -40 °C to 85 °C without violating specifications.
T
PLL_flicker
SKEW
DUTY
ChanX - ChanY
(f) and L
Symbol
f
T
OSCin
T
CLKout
T
V
T
V
T
T
T
SKEW
I
I
T
T
CWH
CWL
OH
OL
CH
EW
OH
OL
CS
ES
R
F
CLK
maximum frequency guaranteed by characterization. Production tested at 200 MHz.
PLL_flat
COMP
(f).
). L
PLL_flat
PLL_flat
(f) is the single side band phase noise measured at an offset frequency, f, in a 1 Hz bandwidth and f
Output High Current (Source)
channel or different channel
LVCMOS to LVPECL skew
Data to Clock Set Up Time
Output Low Current (Sink)
Load Enable Pulse Width
(f) contributes to the total noise, L(f).
Data to Clock Hold Time
LVCMOS outputs, same
LVDS to LVCMOS skew
LVPECL to LVDS skew
Clock Pulse Width High
Skew between any two
Clock Pulse Width Low
CC
Clock to Latch Enable
Maximum Frequency
Output High Voltage
Output Low Voltage
Output Duty Cycle
limits: All clock delays disabled, CLKoutX_DIV = 510, PLL1 and PLL2 locked. (See Table 31 for more information)
Output Rise Time
Output Fall Time
Set Up Time
Parameter
LVCMOS Clock Outputs (CLKoutX)
Microwire Interface Timing
CC
-2 V. 2VPECL: 50 Ω to V
Mixed Clock Skew
T = 25 °C, F
See Microwire Input Timing
See Microwire Input Timing
See Microwire Input Timing
See Microwire Input Timing
See Microwire Input Timing
See Microwire Input Timing
V
MHz, T = 25 °C (Note 39)
V
V
Same device, T = 25 °C,
Same device, T = 25 °C,
Same device, T = 25 °C,
20% to 80%, RL = 50 Ω,
80% to 20%, RL = 50 Ω,
CC
R
CC
CC
20
L
/2 to V
= 50 Ω, C
= 3.3 V, V
= 3.3 V, V
Conditions
1 mA Load
1 mA Load
5 pF Load
CL = 5 pF
CL = 5 pF
(Note 37)
250 MHz
250 MHz
250 MHz
PLL_flicker
CC
CC
CLK
/2, F
-2.36 V. LVDS: 100 Ω differential. LVCMOS: 10 pF.
L
O
O
= 100 MHz.
(f), which is dominant close to the carrier. Flicker noise has a 10
= 10 pF,
CLK
= 1.65 V
= 1.65 V
= 100
PLL_flicker
PLL_flicker
V
(10 kHz) - 20log(Fout / 1 GHz), where L
CC
PLL_flat
Min
250
45
25
25
25
25
25
(f) it is important to be on the 10 dB/decade
8
- 0.1
(f), is defined as: PN1HZ=L
-230
-540
Typ
400
400
770
28
28
50
COMP
is the phase detector
Max
100
0.1
55
PLL_flat
PLL_flicker
PLL_flicker
Units
MHz
mA
mA
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
%
V
V
(f)