lmk04000b National Semiconductor Corporation, lmk04000b Datasheet - Page 26

• Manufacturer Part Number: lmk04000b
• Description: Low-noise Clock Jitter Cleaner With Cascaded Plls
• Manufacturer: National Semiconductor Corporation

www.national.com
14.0 Features
14.1 SYSTEM ARCHITECTURE
The cascaded PLL architecture of the LMK040xx was chosen
to provide the lowest jitter performance over the widest range
of output frequencies and phase noise offset frequencies. The
first stage PLL (PLL1) is used in conjunction with an external
reference clock and an external VCXO to provide a frequency
accurate, low phase noise reference clock for the second
stage frequency multiplication PLL (PLL2). PLL1 typically us-
es a narrow loop bandwidth (10 Hz to 200 Hz) to retain the
frequency accuracy of the reference clock input signal while
at the same time suppressing the higher offset frequency
phase noise that the reference clock may have accumulated
along its path or from other circuits. The “cleaned” reference
clock frequency accuracy is combined with the low phase
noise of an external VCXO to provide the reference input to
PLL2. The low phase noise reference provided to PLL2 allows
it to use wider loop bandwidths (50 kHz to 200 kHz). The cho-
sen loop bandwidth for PLL2 should take best advantage of
the superior high offset frequency phase noise profile of the
internal VCO and the good low offset frequency phase noise
of the reference VCXO for PLL2. Ultra low jitter is achieved
by allowing the external VCXO’s phase noise to dominate the
final output phase noise at low offset frequencies and the in-
ternal VCO’s phase noise to dominate the final output phase
noise at high offset frequencies. This results in best overall
phase noise and jitter performance.
14.2 REDUNDANT REFERENCE INPUTS (CLKin0/
CLKin0*, CLKin1/CLKin1*)
The LMK040xx has two LVDS/LVPECL/LVCMOS compatible
reference clock inputs for PLL1, CLKin0 and CLKin1. The se-
lection of the preferred input may be fixed to either CLKin0 or
CLKin1, or may be configured to employ one of two automatic
switching modes when redundant clock signals are present.
The PLL1 reference clock input buffers may also be individ-
ually configured as either a CMOS buffered input or a bipolar
buffered input.
14.3 PLL1 CLKinX (X=0,1) LOSS OF SIGNAL (LOS)
When either of the two auto-switching modes is selected for
the reference clock input mode, the signal status of the se-
lected reference clock input is indicated by the state of the
CLKinX_LOS (loss-of-signal) output. These outputs may be
configured as either CMOS (active HIGH on loss-of-signal),
NMOS open-drain or PMOS open-drain. If PLL1 was origi-
nally locked and then both reference clocks go away, then the
frequency accuracy of the LMK04000 device will be set by the
absolute tuning range of the VCXO used on PLL1. The ab-
solute tuning range of the VCXO can be determined by mul-
tiplying its' tuning constant by the charge pump voltage.
14.4 INTEGRATED LOOP FILTER POLES
The LMK040xx features programmable 3rd and 4th order
loop filter poles for PLL2. When enabled, internal resistors
and capacitor values may be selected from a fixed range of
values to achieve either 3rd or 4th order loop filter response.
These programmable components compliment external com-
ponents mounted near the chip.
14.5 CLOCK DISTRIBUTION
The LMK040xx features a clock distribution block with a min-
imum of five outputs that are a mixture of LVPECL, 2VPECL,
LVDS, and LVCMOS. The exact combination is determined
by the part number. The 2VPECL is a National Semiconductor
proprietary configuration that produces a 2 Vpp differential
26
swing for compatibility with many data converters. More than
five outputs may be available for device versions that offer
dual LVCMOS outputs.
14.6 CLKout DIVIDE (CLKoutX_DIV, X = 0 to 4)
Each individual clock distribution channel includes a channel
divider. The range of divide values is 2 to 510, in steps of 2.
“Bypass” mode operates as a divide-by-1.
14.7 CLKout DELAY (CLKoutX_DLY, X = 0 to 4)
Each individual clock distribution channel includes a delay
adjustment. Clock output delay registers (CLKoutX_DLY)
support a nominal 150 ps step size and range from 0 to 2250
ps of total delay.
14.8 GLOBAL CLOCK OUTPUT SYNCHRONIZATION
(SYNC*)
The SYNC* input is used to synchronize the active clock out-
puts. When SYNC* is held in a logic low state, the outputs are
also held in a logic low state. When SYNC* goes high, the
clock outputs are activated and will transition to a high state
simultaneously with one another.
SYNC* must be held low for greater than one clock cycle of
the Clock Distribution Path. After this low event has been reg-
istered, the outputs will not reflect the low state for four more
cycles. Similarly after SYNC* becomes high, the outputs will
simultaneously transition high after four Clock Distribution
Path cycles have passed. See Figure 1 for further detail.
14.9 GLOBAL OUTPUT ENABLE AND LOCK DETECT
Each Clock Output Channel may be either enabled or put into
a high impedance state via the Clock Output Enable control
bit (one for each channel). Each output enable control bit is
gated with the Global Output Enable input pin (GOE). The
GOE pin provides an internal pull-up so that if it is un-termi-
nated externally, then the clock output states are determined
by the Clock Channel Output Enable Register bits. All clock
outputs can be disabled simultaneously if the GOE pin is
pulled low by an external signal.
Don't care
CLKoutX
FIGURE 1. Clock Output synchronization using the
_EN bit
1
0
1
TABLE 1. Clock Output Control
EN_CLKout
_Global bit
Don't care
1
0
1
SYNC* pin
Don't care
Don't care
High / No
GOE pin
Connect
Low
Output State
CLKoutX
Enabled
Low
Off
Off
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