lmk04000b National Semiconductor Corporation, lmk04000b Datasheet - Page 29

• Manufacturer Part Number: lmk04000b
• Description: Low-noise Clock Jitter Cleaner With Cascaded Plls
• Manufacturer: National Semiconductor Corporation

16.0 General Programming
Information
LMK040xx devices are programmed using several 32-bit reg-
isters. Each register consists of a 4-bit address field and 28-
bit data field. The address field is formed by bits 0 through 3
(LSBs) and the data field is formed by bits 4 through 31 (MS-
Bs). The contents of each register are clocked in MSB first (bit
To achieve proper frequency calibration, the OSCin port must
be driven with a valid signal before programming Register 15.
Changes to PLL2_R Counter or the OSCin port signal require
Register 15 to be reloaded in order to activate the frequency
calibration process.
16.1 RECOMMENDED PROGRAMMING SEQUENCE
The recommended programming sequence involves pro-
gramming R7 with the reset bit set to 1 (Reg. 7, bit 4) to ensure
the device is in a default state. If R7 is programmed again, the
reset bit should be set to 0. Registers are programmed in or-
der with R15 being the last register programmed. An example
programming sequence is shown below:
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•
Program R7 with the RESET bit = 1 (b4 = 1). This ensures
that the device is configured with default settings. When
RESET = 1, all other R7 bits are ignored.
- If R7 is programmed again during the initial configuration
of the device, the RESET bit should be cleared (b4 = 0)
Program R0 through R4 as necessary to configure the
clock outputs as desired. These registers configure clock
FIGURE 2. uWire Timing Diagram
29
31), and the LSB (bit 0) last. During programming, the LE sig-
nal should be held LOW. The serial data is clocked in on the
rising edge of the CLK signal. After the LSB (bit 0) is clocked
in the LE signal should be toggled LOW-to-HIGH-to-LOW to
latch the contents into the register selected in the address
field. Registers R0-R4, R7, and R8-R15 must be programmed
in order to achieve proper device operation. Figure 2 illus-
trates the serial data timing sequence.
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•
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The following table provides the register map for device pro-
gramming:
channel functions such as the channel multiplexer output
selection, divide value, delay value, and enable/disable
bit.
Program R5 and R6 with the default values shown in the
register map on the following pages.
Program R7 with RESET = 0.
Program R8 through R10 with the default values shown in
the register map on the following pages.
Program R11 to configure the reference clock inputs
(CLKin0 and CLKin1).
- type, LOS timeout, LOS type, and mode (manual or auto-
switching)
Program R12 to configure PLL1.
- Charge pump gain, polarity, R counter and N counter
Program R13 through R15 to configure PLL2 parameters,
crystal mode options, and certain globally asserted
functions.
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