mc145170-2 Freescale Semiconductor, Inc, mc145170-2 Datasheet - Page 10

• Manufacturer Part Number: mc145170-2
• Description: Pll Frequency Synthesizer With Serial Interface
• Manufacturer: Freescale Semiconductor, Inc

Pin Connections
CLK typically switches near 50% of V
times are allowed. See the last paragraph of D
ENB
Active-Low Enable Input (Pin 6)
This pin is used to activate the serial interface to allow the transfer of data to/from the device. When ENB
is in an inactive high state, shifting is inhibited, D
held in the initialized state. To transfer data to the device, ENB (which must start inactive high) is taken
low, a serial transfer is made via Din and CLK, and ENB is taken back high. The low-to-high transition on
ENB transfers data to the C, N, or R register depending on the data stream length per
This input is also Schmitt-triggered and switches near 50% of V
loading erroneous data into the registers. See the last paragraph of D
D
Three-State Serial Data Output (Pin 8)
Data is transferred out of the 16-1/2-stage shift register through Dout on the high-to-low transition of CLK.
This output is a No Connect, unless used in one of the manners discussed below.
Dout could be fed back to an MCU/MPU to perform a wrap-around test of serial data. This could be part
of a system check conducted at power up to test the integrity of the system's processor, PC board traces,
solder joints, etc.
The pin could be monitored at an in-line QA test during board manufacturing.
Finally, D
3.2
OSC
Reference Oscillator Input/Output (Pins 1, 2)
These pins form a reference oscillator when connected to terminals of an external parallel-resonant crystal.
Frequency-setting capacitors of appropriate values as recommended by the crystal supplier are connected
10
out
in
/OSC
Reference Pins
out
facilitates troubleshooting a system and permits cascading devices.
out
To guarantee proper operation of the power-on reset (POR) circuit, the CLK
pin must be held at the potential of either the V
up. That is, the CLK input should not be floated or toggled while the V
pin is ramping from 0 to at least 2.7 V. If control of the CLK pin is not
practical during power up, the initialization sequence shown in
must be used.
Transitions on ENB must not be attempted while CLK is high. This puts the
device out of synchronization with the microcontroller. Resynchronization
occurs when ENB is high and CLK is low.
MC145170-2 Technical Data, Rev. 5
DD
and has a Schmitt-triggered input buffer. Slow CLK rise and fall
in
for more information.
NOTE
NOTE
out
is forced to the high-impedance state, and the port is
SS
DD
or V
, thereby minimizing the chance of
in
DD
for more information.
pin during power
Figure 15
Freescale Semiconductor
Table
DD
7.