mc145170-2 Freescale Semiconductor, Inc, mc145170-2 Datasheet - Page 9

• Manufacturer Part Number: mc145170-2
• Description: Pll Frequency Synthesizer With Serial Interface
• Manufacturer: Freescale Semiconductor, Inc

3
3.1
D
Serial Data Input (Pin 5)
The bit stream begins with the most significant bit (MSB) and is shifted in on the low-to-high transition of
CLK. The bit pattern is 1 byte (8 bits) long to access the C or configuration register, 2 bytes (16 bits) to
access the N register, or 3 bytes (24 bits) to access the R register. Additionally, the R register can be
accessed with a 15-bit transfer (see
Figure
data to the registers is controlled by ENB.
The bit stream needs neither address nor steering bits due to the innovative BitGrabber registers.
Therefore, all bits in the stream are available to be data for the three registers. Random access of any
register is provided (i.e., the registers may be accessed in any sequence). Data is retained in the registers
over a supply range of 2.7 to 5.5 V. The formats are shown in Figures 15, 16, 17, and 18.
D
to CMOS devices with outputs guaranteed to switch near rail-to-rail. When interfacing to NMOS or TTL
devices, either a level shifter (MC74HC14A, MC14504B) or pull-up resistor of 1 to 10 kΩ must be used.
Parameters to consider when sizing the resistor are worst-case I
tolerable power consumption, and maximum data rate.
CLK
Serial Data Clock Input (Pin 7)
Low-to-high transitions on Clock shift bits available at D
D
intermittent mode.
Four to eight clock cycles followed by five clock cycles are needed to reset the device; this is optional.
Eight clock cycles are required to access the C register. Sixteen clock cycles are needed for the N register.
Either 15 or 24 cycles can be used to access the R register (see
cascaded devices, see Figures
Freescale Semiconductor
in
in
out
typically switches near 50% of V
. The chip's 16-1/2-stage shift register is static, allowing clock rates down to dc in a continuous or
15. The values in the C, N, and R registers do not change during shifting because the transfer of
Pin Connections
Digital Interface Pins
Other Values ≤ 32
(MSBs are shifted in first, C0, N0, and R0 are the LSBs)
Values > 32
of Clocks
Number
15 or 24
9 to 13
27
16
8
to 34.
Table
DD
MC145170-2 Technical Data, Rev. 5
to maximize noise immunity. This input can be directly interfaced
Table 7. Register Access
7). An optional pattern which resets the device is shown in
See Figures
See
C Register
N Register
R Register
Accessed
Register
None
Figure 15
27
to
in
34
, while high-to-low transitions shift bits from
Table 7
N15, N14, N13, . . ., N0
R14, R13, R12, . . ., R0
OL
C7, C6, C5, . . ., C0
Nomenclature
of the driving device, maximum
(Reset)
and Figures 15, 16, 17, and 18). For
Bit
Pin Connections
9