mc145170-2 Freescale Semiconductor, Inc, mc145170-2 Datasheet - Page 12

• Manufacturer Part Number: mc145170-2
• Description: Pll Frequency Synthesizer With Serial Interface
• Manufacturer: Freescale Semiconductor, Inc

Pin Connections
When activated, the f
the OSC
buffered and appears at the f
f
N Counter Output (Pin 10)
This signal is the buffered output of the 16-stage N counter. f
(patented). The output is disabled (static low logic level) upon power up. If unused, the output should be
left disabled and unconnected to minimize interference with external circuitry.
The f
is determined by the binary value loaded into the N register. The maximum frequency which the phase
detectors operate is 2 MHz. Therefore, the frequency of f
When activated, the f
3.4
f
Frequency Input (Pin 4)
This pin is a frequency input from the VCO. This pin feeds the on-chip amplifier which drives the N
counter. This signal is normally sourced from an external voltage-controlled oscillator (VCO), and is
ac-coupled into f
size recommended for applications (see
the supply voltage as listed in
frequency is limited to the divide ratio times 2 MHz. (Reason: the phase/frequency detectors are limited
to a maximum frequency of 2 MHz.)
For signals which swing from at least the V
table
frequencies shown in
and may be operated down to dc. However, wave shaping by a CMOS buffer may be required to ensure
fast rise and fall times into the f
Each rising edge on the f
PD
Single-Ended Phase/Frequency Detector Output (Pin 13)
This is a three-state output for use as a loop error signal when combined with an external low-pass filter.
Through use of a patented technique, the detector's dead zone has been eliminated. Therefore, the
phase/frequency detector is characterized by a linear transfer function. The operation of the
phase/frequency detector is described below and is shown in
POL bit (C7) in the C register = low (see
Frequency of f
12
V
in
out
V
on page
signal can be used to verify the N counter's divide ratio. This ratio extends from 40 to 65,535 and
in
Loop Pins
pin signal, except when a divide ratio of 1 is selected. When 1 is selected, the OSC
4, dc coupling may be used. Also, for low frequency signals (less than the minimum
V
> f
in
. A 100 pF coupling capacitor is used for measurement purposes and is the minimum
R
R
V
or Phase of f
Table 6 on page
signal appears as normally low and pulses high. The pulse width is 4.5 cycles of
signal appears as normally low and pulses high.
in
pin causes the N counter to decrement by 1.
R
Table
pin.
in
pin. See
V
6, Loop Specifications. For small divide ratios, the maximum
Leading f
MC145170-2 Technical Data, Rev. 5
7), dc coupling is a requirement. The N counter is a static counter
Figure
Figure
Figure
IL
to V
R
25). The frequency capability of this input is dependent on
: negative pulses from high impedance
16)
25.
IH
levels listed in
V
must not exceed 2 MHz.
V
Figure
can be enabled or disabled via the C register
Table
19.
3, the Electrical Characteristics
Freescale Semiconductor
in
signal is