pll130-69 PhaseLink Corp., pll130-69 Datasheet

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pll130-69

Manufacturer Part Number
pll130-69
Description
High Speed Translator Buffers Single Ended To Pecl Or Lvds - Phaselink Corporation
Manufacturer
PhaseLink Corp.
Datasheet
FEATURES
x Differential PECL (PLL130-68) or LVDS
x Accepts any single-ended REFIN input (with
x Internal AC coupling of REFIN
x Input range from 1.0MHz to 1.0 GHz.
x No Vref required.
x No external current source required.
x 2.5 to 3.3V operation.
x Available in 3x3mm QFN.
DESCRIPTION
The PLL130-68 and PLL130-69 are low cost,
high performance, high speed, translator buffers
that reproduce any input frequency from DC to
1.0GHz. They provide a pair of differential out-
puts (PECL for PLL130-68 or LVDS for PLL130-
69). Thanks to an internal AC coupling of the
reference input (REFIN), any input signal with at
least 100mV swing can be used as reference
signal, regardless of its DC value. These chips
are ideal for conversion from clipped sine wave,
TTL, CMOS, or differential signal to LVDS or
PECL.
BLOCK DIAGRAM
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/09/04 Page 1
(PLL130-69) output.
as low as 100mV swing).
REFIN
Coupling
AC
High Speed Translator Buffers: Single ended to PECL or LVDS
Amplifier
Input
OUTPUT ENABLE LOGICAL LEVELS
PLL130-68
OECTRL input: Logical states defined by PECL levels.
PLL130-69
OECTRL input: Logical states defined by CMOS levels.
0 (Default)
0 (Default)
OESEL
OESEL
1
1
REFIN
PIN CONFIGURATION
NC
NC
NC
0 (Default)
1 (Default)
1 (Default)
0 (Default)
OECTRL
OECTRL
PLL130-68/-69
(TOP VIEW)
1
0
0
1
2
3
1
4
16
PLL130-6x
5
Q
Q_BAR
15
6
14
7
13
8
OUTPUT STATE
OUTPUT STATE
Output enabled
Output enabled
Output enabled
Output enabled
12
11
10
9
Tri-state
Tri-state
Tri-state
Tri-state
NC
Q
Q_bar
OESEL

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pll130-69 Summary of contents

Page 1

... No external current source required. x 2.5 to 3.3V operation. x Available in 3x3mm QFN. DESCRIPTION The PLL130-68 and PLL130-69 are low cost, high performance, high speed, translator buffers that reproduce any input frequency from DC to 1.0GHz. They provide a pair of differential out- puts (PECL for PLL130-68 or LVDS for PLL130- 69) ...

Page 2

... True output. PECL on PLL130-68, LVDS on PLL130-69. P 3.3V Power supply. Additional true output. PECL on PLL130-68, LVDS on PLL130-69. This O output is the same as pin 11. Additional complementary output. PECL_bar on PLL130-68, LVDS_bar O on PLL130-69. This output is the same as pin 10. SYMBOL SYMBOL CONDITIONS Fout = 156.25MHz, PECL I DD Fout = 156.25MHz, LVDS ...

Page 3

... DD V (see figure) OL SYMBOL CONDITIONS t @20/80% - PECL r t @80/20% - PECL f VDD OUT 2.0V 50% OUT PECL Transistion Time Waveform DUTY CYCLE PLL130-68/-69 MIN. TYP. MAX. 0 1000 100 0 1000 MIN. MAX. V – 1.025 V – 0.880 – 1.810 V – 1.620 DD DD MIN. TYP. ...

Page 4

... I OSD SYMBOL CONDITIONS 100 : (see figure) 50 50: LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80 DIFF 20 PLL130-68/-69 MIN. TYP. MAX. 247 355 454 -50 50 1.4 1.6 0.9 1.1 1.125 1.2 1.375 r10 -5.7 -8 MIN. TYP. MAX. 0.2 0.5 1.0 0.2 0.5 1.0 LVDS Switching Test Circuit ...

Page 5

... PLL130-68QC-R PLL130-68QC PLL130-69QC-R PLL130-69QC PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information fur- nished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. ...

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