tda7333 STMicroelectronics, tda7333 Datasheet - Page 12

• Manufacturer Part Number: tda7333
• Description: Rds/rbds Processor
• Manufacturer: STMicroelectronics

TDA7333
12/21
reset value
bit name
re se t v a lue
rds_qu
access
bit na m e
rd s_ in t
a cce ss
(1)
T A
(2)
T A E O N
block D
interrupt source
no interrupt
block A
block B
R D S B lock
block name
bit 7
block C,C'
qu3
block A
block B
block D
w rite
bit 7
0
r/w
r
0
bit 6
qu2
bit 6
bne
0
r
0
r
itsrc2
ar_res
bit 5
bit 5
qu1
r/w
0
0
0
1
1
1
1
0
r
0
blk1
0
0
1
1
synch
bit 4
qu0
bit 4
0
r
0
r
itsrc1
itsrc2
bit 3
blk1
bit 3
0
0
1
0
0
1
1
r/w
0
0
r
blk0
0
1
0
1
itsrc1
bit 2
blk0
bit 2
r/w
0
0
r
itsrc0
itsrc0
bit 1
bit 1
0
1
1
0
1
0
1
r/w
0
0
e
r
bit 0
bit 0
synz
int
0
0
r
r
Note : when changing the interrupt mode, one has to
perform a reset of the module (i.e set the bit “ar_res” at
one)
(3) qu[3..0] is a counter of the quality bit information coming
from the RDS demodulator. It is counting the number of bits
which are marked as bad by the demodulator. Only those bits
are allowed to be corrected. Thus the quality bit counter indi-
cates the maximum possible number of bits being corrected.
It indicates if the error correction was successfull.
1: the syndrome was zero after the error correction.
0: the syndrome did not become zero and therefore the
correction was not successfull.
1: a block E is detected.This indicates a paging block
which is defined in the RBDS specification used in the
united states of America.
0: an ordinary RDS block A, B, C, c´or D is detected, or no
valid syndrome was found.
bit 0 of block counter (2)
bit 1 of block counter (2)
bit 0 of quality counter (3)
bit 1 of quality counter (3)
bit 2 of quality counter (3)
bit 3 of quality counter (3)
interrupt bit. It is set to one on every programmed interrupt. It
is reset by reading rds_int register.
interrupt source
itsrc[2:0] select the interrupt source (1)
synchronization information.
1: the module is already synchronized.
0: the module is synchronizing
It is used to force a resynchronization. If it is set to one, the
RDS modules are forced to resynchronization state.
The bit is automatically reset. So it is always read as zero.
RDS block.
if 1, one block has been detected
rds_int and rds_bd_ctrl write order (when in SPI mode)
1: rds_int and rds_bd_ctrl are updated with data shifted in.
0: rds_int and rds_bd_ctrl are not updated.