tda7333 STMicroelectronics, tda7333 Datasheet - Page 5

• Manufacturer Part Number: tda7333
• Description: Rds/rbds Processor
• Manufacturer: STMicroelectronics

Table 6. Electrical Characteristics (continued)
7
7.1 Overview
The new RDS/RBDS processor contains all RDS/RBDS relevant functions on a single chip. It recovers the
inaudible RDS/RBDS information which are transmitted on most FM radio broadcasting stations.
Due to an integrated 3rd order sigma delta converter, which samples the MPX signal, all further processing
is done in the digital domain and therefore very economical. After filtering the highly oversampled output
of the A/D converter, the RDS/RBDS demodulator extracts the RDS DataClock , RDS Data Signal and
the Quality information. A next RDS/RBDS decoder will synchronize the bitwise RDS stream to a group
and block wise information. This processing includes an error detection and error correction algorithm. In
addition, an automatic flywheel control avoids exhaustive data exchange between the RDS/RBDS proces-
sor and the host.
The device operates in accordance with the EBU (European Broadcasting Union) specifications.
7.2 Sigma Delta Converter
The Sigma Delta Modulator is a 3rd order (second order-first order cascade) structure. Therefore a multibit out-
put (2 bit streams) represents the analog input signal. A next digital noise canceller will take the 2 bit streams
and calculates a combined stream which is then fed to the decimation filter. The modulator works at a sampling
frequency of XTI/2. The oversampling factor in relation to the band of interest (57 kHz +- 2.4 kHz) is 38.
7.3 Sinc4/16 Decimation Filter
The oversampled data delivered from the modulator are decimated by a value of 16 with a 4th order Sinc Filter.
This is considered to be the optimum solution for high decimation factors and for a 3rd order sigma delta mod-
ulator.
I
SPI
2
Symbol
C
f
f
t
f
t
t
R
stop
R
t
t
t
M
SPI
odv
I2C
t
csu
csh
t
t
oh
ch
su
cl
Functional Description
d
h
p
s
i
Passband Ripple
Stopband Corner Frequencies
Stopband Attenuation
Interpolation Factor
clock frequency in I
clock frequency in SPI mode
clock high time
clock low time
chip select setup time
chip select hold
output data valid
output hold
deselect time
data setup time
data hold time
Parameter
2
C mode
Test Conditions
1000
Min.
53.0
-0.5
200
450
450
500
500
200
0
Values
Typ.
-43
32
Max.
+0.5
400
250
61
TDA7333
1
MHz
Unit
kHz
kHz
dB
dB
ns
ns
ns
ns
ns
ns
ns
ns
ns
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