tda7333 STMicroelectronics, tda7333 Datasheet - Page 15

• Manufacturer Part Number: tda7333
• Description: Rds/rbds Processor
• Manufacturer: STMicroelectronics

8
This interface consists of three lines: a serial data line (SDA), a bit clock (SCL), and a slave address select (SA).
The interface is capable of operating in fast mode (up to 400kbits/s) but also at lower rates (<100kbits/s).
Data transfers follow the format shown in Fig.8 . After the START condition (S), a slave address is sent. The
address is 7 bits long followed by an eighth bit which is a data direction bit (R/_W).
A ’zero’ indicates a transmission (WRITE), a ’one’ indicates a request for data (READ).
The slave address of the chip is set to 001000S, where S is the least significant bit of the slave address set
externally via the pin SA_DATAOUT. This allows to choose between two addresses in case of conflict with an-
other device of the radio set.
Each byte has to be followed by an acknowledge bit (SDA low).
Data is transfered with the most significant (MSB) bit first.
A data transfer is always terminated by a stop condition (P) generated by the master.
Figure 10. I
8.1 Write transfer
Figure 11. I
Figure 12. I
SDA
CSN
SCL
SDA
SCL
SA
CONDITION
0
1
START
S
I
S
2
CONDITION
C Transfer Mode
START
S lave address
S
2
2
2
from master to slave
from slave to master
C data transfer
C write transfer
C write operation example : write of rds_int and rds_bd_ctrl registers
SLAVE ADDRESS
ADDRESS
1-7
W
R/W
8
A
W
ACK
ACK
rds_int
9
rds_int[7:0]
1-7
A = acknowledge bit
W = write mode
Slave address = 001000S ( where S is the level of the pin
P = stop condition
S = start condition
A
DATA
r d s_ b d _c trl
8
ACK
A
9
ACK
sinc4reg
SA_DATAOUT)
1-7
rds_bd_ctrl[7:0]
DATA
A
8
testreg
ACK/ACK
9
ACK
A
TDA7333
CONDITION
STOP
CONDITION
P
P
STOP
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P