ad2s46 Analog Devices, Inc., ad2s46 Datasheet - Page 5

• Manufacturer Part Number: ad2s46
• Description: Low Cost, L6-bitsynchro Resolver -to-digital Converte
• Manufacturer: Analog Devices, Inc.

ANALOG DEVICES fAX-ON-DEMAND HOTLINE
according to the following convention:
It is recommended that the resolver is connected using individu-
ally screened twisted pair cables with the sine, cosine and refer-
ence signals twisted separately.
REV. 0
For a resolver, the signals are connected to 51, 52, 53 and 54
supply pins to GND.
The digital output is taken from Pins 21-28 and Pins 1-8.
Pin 21 is the MSB, Pin 8 the L5B.
The reference connections are made to REF HI and REF LO.
In the case of a synchro, the signals are connected to $1, 52 and
53 according to the following convention:
It is suggested that a parallel combination of a 100 nF (ceramic)
and a 6.8 fLF(tantalum) capacitor be placed from each of the
The power supply voltages connected to -Y sand + Vspins
CONNECTING
should be -15 Yand + 15 Y and must nor be reversed.
E52-54
E53.52
E52-51 = ERLO..RHI s in wt sin (0 + 240°)
ESJ-S3 "" ERLORHI
Es I-S3
=
=
=
ERLO-RHI sin wt sin e
ERLO-RHIsin wt sin (6 -+-120°)
ERLO-RHI sin wt cos
THE CONVERTER
PHASELAG= ARCTAN
OPTIONAL PHASE SHIFT CIRCUITS
sin wt sin
~AAE
~
o--f
~
e
e
C
,t~N
-
Page
R
-
2" IRC
>. me
16
1
Figure 1.
------
Connection
LS BYTE
OUTPUT
-5-
DATA
logic "HI" maintains the OUtpUtdata pins in the high imped-
ance state, and application of a logic "LO" presents the data of
shown in Figure 2.
ENABLE INPUT
The ENABLE input determines rhe state of the omput data. A
the latches to the outpUt pins. The operation of the ENABLE
has no effect on the conversion process. Timing information is
INHIBIT aUtomatically generates a refresh of the output data.
DATA TRANSFER
To transfer data the i"NH1BIT input should be used. The data
will be valid 600 liS after the application of a logic "LO" to
INHIBIT. By using the ENABLE inpUt the two bytes of data
can be transferred after which the INHIBIT should be retUrned
to a logic "HI" Slate to enable the oUtpUtlarches to be updated.
INHIBIT INPUT
The INHIBIT logic input only inhibits the data transfer from
the up-down coumer to the outpUt latches and, therefore, does
not interrupt the operation of the tracking loop. Releasing the
PHASE
LEAD!
LAG
Diagram
AD2S46
100nF
(E.G., ose 1758)
OSCILLATOR
OUTPUT
DATA
MS BYTE
100k
ov
+15V
-15V
AD2S46