ad2s46 Analog Devices, Inc., ad2s46 Datasheet - Page 6

• Manufacturer Part Number: ad2s46
• Description: Low Cost, L6-bitsynchro Resolver -to-digital Converte
• Manufacturer: Analog Devices, Inc.

channel wires and the cosine channel wires are treated differ-
ently. For instance, different cable lengths or different capactive
loads could cause differential phase shifr. The additional error
CAUSES OF ERROR
Differential Phase Shift
solver is known as differential phase shift and can cause static
errors. Some differential phase shift will be present on all resolv-
ers being a characteristic of the transducer. A small resolver re-
sidual voltage (quadratUre voltage) indicates a small differential
phase shift. Additional phase shift can be introduced if the sine
caused by differential phase shift on the input signals approXi-
mates to:
A logic LO on the BYTE SELECT place the LS BYTE at
Pins 21 to 28 (LSB). Using the ENABLE, the parallel data is
presented to the bus.
The operation of the BYTE SELECT has no effect on the con-
version process of the convener.
REFERENCE INPUT
The amplitude of the reference signal applied to the converter's
input is not critical, but care should be taken to ensure it is
within the recommended operating conditions.
The AD2S46 will not be damaged if the reference is supplied
to the convener without the power supplies and/or the signal
inputs.
Phase shift betWeen the sine and the cosine signals from the re-
must take place. The BYTE SELECT pin at logic HI places the
parallel data is presented to the bus.
9 to Bit 16 LSB, respectively). The ENABLE control is used to
present the digital 16-bit parallel digital output position data to
the pins.
To interface to an 8-bit parallel bus, tWo sequential readiogs
MS BYTE at Pins 21 (MSB) to 28. Using the ENABLE, the
AD2S46
BYTE SELECT INPUT
The BYTE SELECT input on the AD2S46 can be used to inter-
face the converter to either an 8-bit or 16.bit microprocessor
bus.
To interface to a 16-bit parallel bus, the BYTE SELECT pin
should be at logic HI. Thus, the most significant byte of the
digital output position is at Pins 21 to 28 (Bit 1 MSB to Bit 8,
respectively). Also the least significant byte is at Pin I to 8 (Bit
RNRLOGDEVICES fRK-ON-DEMRND HOTLINE
BYTE SELECT
ENABLE
INHIBIT
DATA
DATA
DATA
~
Error
Figure 2. Timing Diagrams
==
0.53 x a x b arc minuleS
+ct
t:l
LS BYTE
DATA VAUD
-
Page
17
;-
-6-
matching accuracies of resistors used for external scaling. For
resistor values will contribute an additional 1.7 arc minutes of
error to the conversion. In addition, imbalances in resistor val-
ues can greatly reduce the common-mode rejection ratio of the
signal inputs.
signal and reference voltages which are outside the nominal
encountered.
NOTE: The accuracy of the converter will be affected by the
resolver format options, it is critical that the value of the resis-
tOrs on the Sl-83 signal input pair be precisely matched to the
54-52 inpUt pair. For synchro options, the three resistors on 51,
52, S3 must be matched. In general, a 0.1% mismatch between
SCALING FOR NONSTANDARD
A feature of these converters is that the signal and reference in-
puts can be resistively scaled to accommodate nonstandard input
ble to use a standard convener with a "personality card" in sys-
tems where a wide range of input and reference voltages are
convener's stated accuracy. However, most resolvers exhibit a
error derIDed by
This effect can be eliminated by placing a phase lead/lag
ING THE CONVERTER").
NOTE:
reference leads can cause similar conditions as described above.
== 10% limits of the convener. Using this technique, it is possi-
residual voltage, ensuring that the sine and cosine signals are
shift (see section on "CONNECTING THE CONVERTER").
Resolver Phase Shift
ence and the signal lines alone will not theoretically affect the
phase shift between the signal and the reference. This phase
shift will give rise under dynamic conditions to an additional
netWork on the reference signal to the converter equivalent to
the phase shift caused by the resolver (see section "CONNECT-
where a
and b
This error can be minimized by choosing a resolver with a small
routed identically and removing the reference/signals phase
By taking these precautions, the extra error can be made
insignificant.
Under static operating conditions phase shift between the refer-
i 12
i13
i
:
r
i
r
==
Biaary
Bits (N)
10
II
14
15
16
17
18
.s-t-
0
2
3
4
6
7
8
9
I
==
Capacitive and inductive crosstalk in the signal and
signal to referencephase shift in degrees.
differentialphase shift in degrees
Shaft Speed irpsl x Phase Shift (tkgrees)
J
I
i
!
262144
R..olutioa
(2")
131072
16384
32768
65536
1024
2048
4096
8192
256
512
128
64
32
16
4
8
1
2
Reference Frequency
Bit Weight Table
' 45.0
i
j
j 11.25
Degrees
/Bit
360.0
180.0
90.0
22.5
0.703125
0.3515625
0.1757813
0.0878906
0.0439453
0.0219727
0.0109836
0.0054932
0.0027466
0.0013733
5.625
2.8125
J.4O625
1
i 10800.0
i
i
..."'.
/Bit
Miautes
21600.0
2700.0
5400.0
1350.0
675.0
337.5
168.75
84.375
42.1875
21.09375
10.5<Hi875
SIGNALS
0.659180
0.164795
0.329590
5.273438
2.636719
1.318359 i
0.082397
!
!
i
i
;
!
I
!
Seconds
/Bit
1296000.0
&48000.0
162000.0
24000.0
81000.0
oW5oo.0
20250.0
10125.0
5062.5
2531.25
1265.625
632.8125
316.40625
158.20313
79.10156
39.55078
19.77539
9.88770
4.94385
.,-
REV.0
,
;