hsp48908 Intersil Corporation, hsp48908 Datasheet - Page 8

• Manufacturer Part Number: hsp48908
• Description: Two Dimensional Convolver
• Manufacturer: Intersil Corporation

EALU
The EALU control pin enables loading of the ALU Register.
While the EALU line is high, the data on ClN0-7 is latched
into the ALU Register on the rising edge of CLK. When
EALU goes low, the current value in the ALU Register is held
until EALU is again asserted. Note that the ALU loading
operation makes use of the ClN0-7 inputs, but is completely
independent of CS and LD. Therefore, in order to prevent
overwriting an internal register, care must be taken to ensure
that CS and LD are not active during an EALU cycle.
Programmable Row Buffers
The programmable row buffers are used for buffering raster
input data for the convolution operation. They can be thought
of as Programmable Shift Registers which can each store up
to 1024 8-bit values, thus, delaying each pixel by up to 1024
clock cycles. Functionally, each row buffer can be
represented as a set of registers connected as a 1024 x 8-bit
Serial Shift Register. The output of each buffer can be
represented by the equation Q = D(n-r), where Q is the row
buffer output, D is the buffer input, n is the current clock
cycle and r is the preprogrammed row length of the input
image. Since the two buffers are connected in series, the
data at the cascade outputs (CASO0-7) is delayed by two
row delays and may be used for cascading multiple
convolvers for larger kernel sizes and/or row lengths. The
programmable row buffers can also be bypassed by
selecting the appropriate cascade mode in the Initialization
Register. This mode allows the use of external row buffers
for convolving with row lengths longer than 1024 pixels.
6
0
0
1
1
1
1
0
1
5
1
1
0
1
1
0
1
0
TABLE 2. ALU PIXEL OPERATIONS (Continued)
REGISTER BIT
4
0
1
1
0
1
0
1
0
3
0
1
1
1
0
0
0
1
2
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
Logical (A AND B)
Logical (A OR B)
Logical (A OR B)
Logical (A OR B)
Logical (A NAND B)
Logical (AN OR B)
Logical (A XOR B)
Logical (A XNOR B)
OPERATION
HSP48908
8-BIt Multiplier Array
The multiplier array consists of nine 8 x 8 multipliers. Each
multiplier forms the product of a filter coefficient with a
corresponding pixel in the input image. Input and coefficient
data may be in either two’s complement or unsigned integer
format. The nine coefficients form a 3 x 3 filter kernel which
is multiplied by the input pixel data and summed to form a
sum of products for implementation of the convolution
operation as shown below:
OUTPUT =
Control Logic
The control logic (Figure 1) contains the ALU Microcode
Register, the Initialization Register, the Row Length Register,
and the Coefficient Registers. The control logic is updated
by placing data on the CIN0-9 bus and using the A0-2, CS
and LD control lines to write to the Addressed Register (see
Address Decoder). All of the Control Logic Registers are
loaded with their default values on RESET, and are
unaffected by FRAME.
ALU Microcode Register
The ALU Microcode Register is used to store the command
word for the ALU. The ALU command word is a 10-bit
instruction divided into two fields: the lower 7 bits determine
the ALU operation and the upper 3 bits specify the number
of shifts which occur. The ALU command words are defined
in Tables 1 and 2 (See ALU Section).
P1
P4
P7
INPUT DATA
(A x P1)
+ (D x P4)
+ (G x P7)
P2
P5
P8
+ (B x P2)
+ (E x P5)
+ (H x P8)
P3
P6
P9
FILTER KERNEL
+ (C x P3)
+ (F x P6)
+ (l x P9)
A B C
D E F
G H I