hsp48908 Intersil Corporation, hsp48908 Datasheet - Page 7

• Manufacturer Part Number: hsp48908
• Description: Two Dimensional Convolver
• Manufacturer: Intersil Corporation

Functional Description
The HSP48908 two-dimensional convolver performs
convolution of 3 x 3 filter kernels. It accepts the image data
in raster scan, non-interlaced format, convolves it with the
filter kernel and outputs the filtered image. The input and
filter kernel data are both 8 bits, while the output data is 20
bits to prevent overflow during the convolution operation.
The HSP48908 has internal storage for two 3 x 3 filter
kernels and is capable of buffering two 1024 x 8-bit rows for
true single chip operation at video frame rates. An 8-bit ALU
in the input pixel data path allows the user to perform
arithmetic and logical operations on the input data in real
time during the convolution. Multiple devices can also be
cascaded together for larger kernel convolution, larger frame
sizes and increased precision.
Image data is input to the convolver via the DIN0-7 bus. The
data is then operated on by the ALU, stored in the row
buffers and convolved with the 3 x 3 array of filter
coefficients. The resultant output data is then latched into
the Output Register. The row buffers are preprogrammed to
the length of one row of the input image to enable the user to
input the image data one pixel at a time in raster scan format
without having to provide external storage.
Initialization of the convolver is done using the ClN0-7 bus to
load configuration data, such as the filter kernel(s) and the
length of the row buffers. The address lines A0-2 are used to
address the Internal Registers for initialization. The
configuration data is loaded using the A0-2, CIN0-9, CS and
LD controls as address, data, chip select and write enable,
respectively. This interface is compatible with standard
microprocessors without the use of any additional glue logic.
Filtered image data comes out of the convolver over the
DOUT0-1 9 bus. This output bus is 20 bits wide to provide
room for growth during the convolution operation. The 20-bit
bus will allow the use of up to 4 x 4 kernels (using multiple
48908s) without overflow. However, in practical applications,
much larger kernel sizes can be implemented without
overflow since the filter coefficients are typically much
smaller than 8-bit full scale values. DOUT0-19 is also a
registered, three state bus to facilitate cascading multiple
chips and to allow the HSP48908 to reside on a standard
microprocessor system bus.
Multiple convolvers can also be cascaded together for kernel
sizes larger than 3 x 3 and for convolution on images with
row lengths longer than 1024 pixels. The maximum kernel
size is dependent upon the magnitude of the image data and
the coefficients in a given application; care must always be
taken with very large kernel sizes to prevent overflow of the
20-bit output.
Data Input
Image data coming into the 2D Convolver passes through a
programmable pipeline delay before being sent to the ALU.
The amount of delay (1 to 4 clock cycles) is set in the
7
HSP48908
Initialization Register during configuration setup (See
Control Logic). Delays greater than one are used primarily in
cascading multiple HSP48908s to align data sequences for
proper output (See Operation).
Arithmetic Logic Unit
The on-chip ALU provides the user with the capability of
performing pixel point operations on incoming image data.
Depending on the instruction in the ALU Microcode Register,
the ALU can perform any one of 19 arithmetic and logical
functions, and shift the resulting number left or right by up to
3 bits. Tables 1 and 2 show the available ALU functions and
the 10-bit associated microcode to be loaded into the ALU
Microcode Register. Note that the shifts take place on the
output of the ALU and are completely independent of the
logical or arithmetic operation being performed. The first
input (A) of the ALU is taken from the pixel input bus (DlN0-
7). The second input (B) is taken from the ALU Register. The
ALU Register is loaded via the ClN0-7 bus while the EALU
control line is valid (see EALU).
6
0
1
0
0
1
1
0
1
1
0
0
REGISTER BIT
9
0
0
0
0
1
1
1
I
5
0
1
0
1
1
0
1
0
0
0
0
8
0
0
1
1
0
0
1
1
REGISTER BIT
4
0
1
1
0
0
1
1
0
0
0
1
TABLE 1. ALU SHIFT OPERATIONS
TABLE 2. ALU PIXEL OPERATIONS
7
0
1
0
1
0
1
0
1
3
0
1
1
1
0
0
0
1
1
1
0
ALU MICROCODE REGISTER
No Shift (Default)
Shift Right 1
Shift Right 2
Shift Right 3
Shift Left 1
Shift Left 2
Shift Left 3
Not Valid
2
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
Logical (00000000)
Logical (11111111)
Logical (A) (Default)
Logical (B)
Logical (A)
Logical (B)
Arithmetic (A + B)
Arithmetic (A -B)
Arithmetic (B -A)
Logical (A AND B)
Logical (A AND B)
OPERATION
OPERATION