pcf8566 NXP Semiconductors, pcf8566 Datasheet - Page 19

• Manufacturer Part Number: pcf8566
• Description: Universal Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

Philips Semiconductors
7.5
The PCF8566 acts as an I
not initiate I
master receiver. The only data output from the PCF8566
are the acknowledge signals of the selected devices.
Device selection depends on the I
on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress
inputs A0, A1 and A2 are normally left open-circuit or tied
to V
In multiple device applications A0, A1 and A2 are left
open-circuit or tied to V
coding scheme such that no two devices with a common
I
subaddress.
In the power-saving mode it is possible that the PCF8566
is not able to keep up with the highest transmission rates
when large amounts of display data are transmitted. If this
situation occurs, the PCF8566 forces the SCL line LOW
until its internal operations are completed. This is known
as the ‘clock synchronization feature’ of the I
serves to slow down fast transmitters. Data loss does not
occur.
7.6
To enhance noise immunity in electrically adverse
environments, RC low-pass filters are provided on the
SDA and SCL lines.
7.7
Two I
reserved for PCF8566. The least-significant bit of the slave
address that a PCF8566 will respond to is defined by the
level tied at its input SA0 (pin 10). Therefore, two types of
PCF8566 can be distinguished on the same I
allows:
1. Up to 16 PCF8566s on the same I
2. The use of two types of LCD multiplex on the same
1998 May 04
2
C-bus slave address have the same hardware
Universal LCD driver for low multiplex
rates
SS
LCD applications
I
2
2
C-bus.
C-bus slave addresses (0111110 and 0111111) are
which defines the hardware subaddress 0.
PCF8566 I
Input filters
I
2
C-bus protocol
2
C-bus transfers or transmit data to an I
2
C-bus controller
SS
or V
2
C-bus slave receiver. It does
DD
according to a binary
2
C-bus slave address,
2
C-bus for very large
2
2
C-bus which
C-bus and
2
C-bus
19
The I
initiated with a START condition (S) from the I
master which is followed by one of the two PCF8566 slave
addresses available. All PCF8566s with the corresponding
SA0 level acknowledge in parallel the slave address but all
PCF8566s with the alternative SA0 level ignore the whole
I
command bytes (m) follow which define the status of the
addressed PCF8566s. The last command byte is tagged
with a cleared most-significant bit, the continuation bit C.
The command bytes are also acknowledged by all
addressed PCF8566s on the bus.
After the last command byte, a series of display data bytes
(n) may follow. These display data bytes are stored in the
display RAM at the address specified by the data pointer
and the subaddress counter. Both data pointer and
subaddress counter are automatically updated and the
data are directed to the intended PCF8566 device.
The acknowledgement after each byte is made only by the
(A0, A1, A2) addressed PCF8566. After the last display
byte, the I
7.8
The command decoder identifies command bytes that
arrive on the I
continuation bit C in their most-significant bit position
(see Fig.16). When this bit is set, it indicates that the next
byte of the transfer to arrive will also represent a
command.
If the bit is reset, it indicates the last command byte of the
transfer. Further bytes will be regarded as display data.
The five commands available to the PCF8566 are defined
in Table 5.
2
C-bus transfer. After acknowledgement, one or more
2
C-bus protocol is shown in Fig.15. The sequence is
Command decoder
2
C-bus master issues a STOP condition (P).
2
C-bus. All available commands carry a
Product specification
PCF8566
2
C-bus