pcf8534 NXP Semiconductors, pcf8534 Datasheet - Page 19

• Manufacturer Part Number: pcf8534
• Description: Universal Driver Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
7. Application design-in information
PCF8534_0
Preliminary datasheet
7.1 Characteristics of the I
7.2 Bit transfer
7.3 START and STOP conditions
7.4 System configuration
The I
The two lines are a Serial Data line (SDA) and a Serial Clock Line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer is initiated only when the bus is not busy.
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable during the HIGH period of the clock pulse as
changes in the data line at this time will be interpreted as a control signal. Bit transfer is
illustrated in
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW
transition of the data line, while the clock is HIGH is defined as the START condition (S).
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition (P). The START and STOP conditions are illustrated in
A device generating a message is a ‘transmitter’, a device receiving a message is the
‘receiver’. The device that controls the message is the ‘master’ and the devices which are
controlled by the master are the ‘slaves’. The system configuration is illustrated in
Figure
Fig 11. Bit transfer
Fig 12. Definition of START and STOP conditions
2
C-bus is for bidirectional, two-line communication between different ICs or modules.
SDA
SCL
13.
Figure
START condition
SDA
SCL
11.
S
Rev. 00.05 — 20 February 2007
2
C bus
data valid
data line
stable;
Universal LCD driver for low multiplex rates
change
allowed
of data
STOP condition
Figure
mba607
P
PCF8534
© NXP B.V. 2007. All rights reserved.
12.
mbc622
SDA
SCL
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