pcf8534 NXP Semiconductors, pcf8534 Datasheet - Page 21

• Manufacturer Part Number: pcf8534
• Description: Universal Driver Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF8534_0
Preliminary datasheet
7.7 Input filters
7.8 I
In single device application, the hardware subaddress inputs A0, A1 and A2 are normally
tied to V
A0, A1 and A2 are tied to V
that no two devices with a common I
subaddress.
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
Two I
The least significant bit of the slave address that a PCF8534 will respond to is defined by
the level tied at its input SA0. The PCF8534 is a write only device and will not respond to
a read access. Therefore, two types of PCF8534 can be distinguished on the same
I
The I
condition (S) from the I
addresses available. All PCF8534’s with the corresponding SA0 level acknowledge in
parallel to the slave address, but all PCF8534’s with the alternative SA0 level ignore the
whole I
After acknowledgement, a control byte follows which defines if the next byte is RAM or
command information. The control byte also defines if the next following byte is a control
byte or further RAM/command data.
In this way it is possible to configure the device then fill the display RAM with little
overhead.
The command bytes and control bytes are also acknowledged by all addressed
PCF8534’s connected to the bus.
The display bytes are stored in the display RAM at the address specified by the data
pointer and the subaddress counter. Both data pointer and subaddress counter are
automatically updated and the data is directed to the intended PCF8534 device.
The acknowledgement after each byte is made only by the (A0, A1 and A2) addressed
PCF8534. After the last display byte, the I
Alternatively a START may be issued to RESTART an I
2
2
1. Up to 16 PCF8534’s on the same I
2. The use of two types of LCD multiplex on the same I
C-bus which allows:
C-bus protocol
2
2
C-bus protocol is shown in
C-bus slave addresses (01110000 and 01110010) are reserved for the PCF8534.
2
C-bus transfer.
SS
which defines the hardware subaddress 0. In multiple device applications
Rev. 00.05 — 20 February 2007
2
C-bus master which is followed by one of the two PCF8534 slave
SS
or V
Figure
DD
2
C-bus slave address have the same hardware
in accordance with a binary coding scheme such
2
C-bus for very large LCD applications
15. The sequence is initiated with a START
2
Universal LCD driver for low multiplex rates
C-bus master issues a STOP condition (P).
2
C-bus access.
2
C-bus.
PCF8534
© NXP B.V. 2007. All rights reserved.
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