pcf85176 NXP Semiconductors, pcf85176 Datasheet
pcf85176
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pcf85176 Summary of contents
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... Universal LCD driver for low multiplex rates Rev. 01 — 14 April 2010 1. General description The PCF85176 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) multiplexed LCD containing up to four backplanes and segments. It can be easily cascaded for larger LCD applications. The PCF85176 is compatible with most ...
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... AND TIMING SYNC OSC OSCILLATOR V DD SCL INPUT FILTERS SDA Fig 1. Block diagram of PCF85176 PCF85176_1 Product data sheet Ordering information Package Name Description TQFP64 plastic thin quad flat package, 64 leads; body 10 × 10 × 1.0 mm TSSOP56 plastic thin shrink small outline package, 56 leads; ...
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... SYNC 13 CLK OSC Top view. For mechanical details, see Pinning diagram for TQFP64 (PCF85176H) All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Universal LCD driver for low multiplex rates PCF85176H 013aaa069 Figure 25. 48 n.c. 47 S17 ...
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... S20 24 S21 25 26 S22 27 S23 S24 28 Top view. For mechanical details, see Pinning diagram for TSSOP56 (PCF85176T) All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Universal LCD driver for low multiplex rates 56 BP0 55 V LCD ...
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... All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Universal LCD driver for low multiplex rates Description Type 2 input/output I C-bus serial data line 2 input I C-bus serial clock ...
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... LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and segments. The possible display configurations of the PCF85176 depend on the number of active backplane outputs required. A selection of display configurations is shown in of these configurations can be implemented in the typical system shown in Table 4 ...
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... LCD off(RMS) > LCD th ⁄ 1 bias are possible but the discrimination and 2 Equation PCF85176 RMS D = ------------------------ - off RMS ∞ 2.236 2.236 1.915 1.732 1: (1) © NXP B.V. 2010. All rights reserved. ...
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... Universal LCD driver for low multiplex rates to V and is determined from off(RMS) × 2.449V = ( ) ( off RMS off RMS ( × --------------------- - 2.309V = ( ) off RMS 3 ⁄ 1 when bias is used PCF85176 Equation 2: (2) Equation 3: (3) LCD ) © NXP B.V. 2010. All rights reserved ...
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... BP0 off(RMS) Static drive mode waveforms All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 (on) (off) 013aaa207 © NXP B.V. 2010. All rights reserved. ...
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... NXP Semiconductors 7.4.2 1:2 Multiplex drive mode When two backplanes are provided in the LCD, the 1:2 multiplex mode applies. The PCF85176 allows the use of Figure 7. Fig 6. PCF85176_1 Product data sheet ⁄ bias LCD V /2 BP0 LCD LCD BP1 V /2 LCD V SS ...
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... BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:2 multiplex drive mode with All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms 013aaa209 at LCD segment ...
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... BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:3 multiplex drive mode with All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Universal LCD driver for low multiplex rates T fr LCD segments state 1 state 2 (a) Waveforms at driver. (b) Resultant waveforms 013aaa210 at LCD segment ...
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... Sn BP1 V = 0.333V . off(RMS) LCD Waveforms for the 1:4 multiplex drive mode with All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Universal LCD driver for low multiplex rates T fr state 1 state 2 013aaa211 at LCD segment. ⁄ 1 bias 3 LCD segments © ...
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... NXP Semiconductors 7.5 Oscillator 7.5.1 Internal clock The internal logic of the PCF85176 and its LCD drive signals are timed either by its internal oscillator external clock. The internal oscillator is enabled by connecting pin OSC to pin V as the clock signal for several PCF85176 in the system that are connected in cascade. ...
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... BP3 respectively. Fig 10. Display RAM bit map When display data is transmitted to the PCF85176 the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for an acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triples or quadruples ...
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LCD segments LCD backplanes S a n+2 BP0 n+3 n+1 static n+5 n n+6 BP0 1 ...
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... The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCF85176 occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character ...
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... In static mode, row 0 is selected The PCF85176 includes a RAM bank switching feature in the static and 1:2 multiplex drive modes. In the static drive mode, the bank-select command may request the contents of row selected for display instead of the contents of row 0. In the 1:2 multiplex mode, the contents of rows 2 and 3 may be selected instead of rows 0 and 1 ...
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... C-bus SDA SCL data line stable; data valid Figure 13). All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Universal LCD driver for low multiplex rates f clk --------- - 768 f clk ------------ - 1536 f clk ------------ - 3072 ). For the range of the clock frequency see ...
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... Product data sheet S START condition MASTER SLAVE TRANSMITTER/ RECEIVER RECEIVER 2 C-bus is illustrated in All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Universal LCD driver for low multiplex rates P STOP condition Figure 14). SLAVE MASTER TRANSMITTER/ TRANSMITTER RECEIVER Figure 15 ...
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... Bit The PCF85176 is a write-only device and will not respond to a read access, therefore bit 0 should always be logic 0. Bit 1 of the slave address byte that a PCF85176 will respond to, is defined by the level tied to its SA0 input (V Having two reserved slave addresses allows the following on the same I ...
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... The I C-bus protocol is shown in condition (S) from the I slave addresses available. All PCF85176 whose SA0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. This I ignored by all PCF85176 whose SA0 inputs are set to the alternative level. Fig 16. I After an acknowledgement, one or more command bytes follow that define the status of each addressed PCF85176 ...
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... NXP Semiconductors 7.17 Command decoder The command decoder identifies command bytes that arrive on the I The commands available to the PCF85176 are defined in Table 8. Bit position labelled not used. Command Bit mode-set load-data-pointer device-select bank-select blink-select All available commands carry a continuation bit C in their most significant bit position as shown in transfer to arrive will also represent a command ...
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... All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Universal LCD driver for low multiplex rates 1:2 multiplex RAM bits 0 and 1 RAM bits 2 and 3 RAM bits 0 and 1 RAM bits 2 and 3 [1] [2] © NXP B.V. 2010. All rights reserved. ...
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... A0 LCD BP0, BP1, BP2, BP3 LCD S0 to S39 V SS All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 SCL V SS SDA LCD V SS mdb076 © NXP B.V. 2010. All rights reserved ...
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... Ref. 8 “JESD78” All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Universal LCD driver for low multiplex rates ) is off, or vice versa. This may cause unwanted DD and V must be applied or removed together. ...
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... [5][6] 0. − − −100 - [8] - 1.5 - 6.0 2 C-bus inactive. limiting values given in I PCF85176 Max Unit 5.5 V 6.5 V μA 20 μA 60 1 μA +1 μ +100 mV - kΩ - kΩ Table 15 (see Figure 18 © NXP B.V. 2010. All rights reserved. ...
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... T = 1.536 kHz; all RAM written with logic 1; no display connected. amb clk(ext) with respect to V DD(LCD) All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Universal LCD driver for low multiplex rates 001aal523 ( 1.536 kHz ...
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... C; unless otherwise specified. Min Typ [1] 1440 1970 960 - [ 1.3 - 0.6 - 100 - 0 - 1.3 - 0.6 - 0 PCF85176 Max Unit 2640 Hz 2640 Hz 110 Hz 110 Hz μs - μ μs - μs 30 400 kHz μs - μ μs - μs - μs - μs - μs 0.3 μs 1.0 μs 0.3 400 and V with © ...
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... CLK SYNC t PD(SYNC_N) t SYNC_NL t PD(drv BUF LOW t HD;STA 2 C-bus timing waveforms All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Universal LCD driver for low multiplex rates t clk( HD;DAT t HIGH t SU;STA ...
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... NXP Semiconductors 12. Application information 12.1 Cascaded operation Large display configurations PCF85176 can be recognized on the same 2 I C-bus by using the 3-bit hardware subaddress (A0, A1, and A2) and the programmable 2 I C-bus slave address (SA0). Table 18. Cluster 1 2 When cascaded PCF85176 are synchronized, they can share the backplane signals from one of the devices in the cascade ...
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... A PCF85176 asserts the SYNC line at the onset of its last active backplane signal and monitors the SYNC line at all other times. If synchronization in the cascade is lost restored by the first PCF85176 to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for the various drive modes of the PCF85176 are shown in The contact resistance between the SYNC on each cascaded device must be controlled ...
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... OSC connected to V must be ensured that the clock tree is designed such that on all PCF85176 the clock propagation delay from the clock source to all PCF85176 in the cascade is as equal as possible since otherwise synchronization artefacts may occur. ...
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... NXP Semiconductors Fig 24. Synchronization of the cascade for the various PCF85176 drive modes PCF85176_1 Product data sheet Universal LCD driver for low multiplex rates BP0 SYNC (a) static drive mode. BP0 (1/2 bias) BP0 (1/3 bias) SYNC (b) 1:2 multiplex drive mode. BP0 (1/3 bias) SYNC (c) 1:3 multiplex drive mode. ...
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... UNIT max. 0.15 1.05 mm 1.2 0.25 0.05 0.95 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT357-1 137E10 Fig 25. Package outline SOT357-1 (TQFP64) of PCF85176H PCF85176_1 Product data sheet ...
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... Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION IEC SOT364-1 Fig 26. Package outline SOT364-1 (TSSOP56) of PCF85176T PCF85176_1 Product data sheet 2.5 scale (1) (2) b ...
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... Inspection and repair • Lead-free soldering versus SnPb soldering PCF85176_1 Product data sheet Universal LCD driver for low multiplex rates All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 © NXP B.V. 2010. All rights reserved ...
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... Volume (mm ) < 350 260 260 250 Figure 27. All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Universal LCD driver for low multiplex rates Figure 27) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 ...
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... Root Mean Square Serial Clock Line Serial DAta Line Surface-Mount Device All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Universal LCD driver for low multiplex rates peak temperature © NXP B.V. 2010. All rights reserved. time 001aac844 ...
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... Universal LCD driver for low multiplex rates 2 C-bus specification and user manual Data sheet status Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Change notice Supersedes - - © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors’ warranty of the All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Universal LCD driver for low multiplex rates © NXP B.V. 2010. All rights reserved ...
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... I C-bus — logo is a trademark of NXP B.V. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 01 — 14 April 2010 PCF85176 Universal LCD driver for low multiplex rates © NXP B.V. 2010. All rights reserved ...
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... Package outline Handling information . . . . . . . . . . . . . . . . . . . 37 Soldering of SMD packages . . . . . . . . . . . . . . 37 Introduction to soldering Wave and reflow soldering Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 38 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 38 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 39 References Revision history . . . . . . . . . . . . . . . . . . . . . . . 40 Legal information . . . . . . . . . . . . . . . . . . . . . . 41 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 41 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Contact information . . . . . . . . . . . . . . . . . . . . 42 Contents Date of release: 14 April 2010 Document identifier: PCF85176_1 All rights reserved. ...