pcf85176 NXP Semiconductors, pcf85176 Datasheet - Page 17

• Manufacturer Part Number: pcf85176
• Description: Universal Lcd Driver For Low Multiplex Rates
• Manufacturer: NXP Semiconductors

NXP Semiconductors
PCF85176_1
Product data sheet
7.12 Subaddress counter
7.11 Data pointer
The following applies to
The addressing mechanism for the display RAM is realized using the data pointer. This
allows the loading of an individual display data byte, or a series of display data bytes, into
any location of the display RAM. The sequence commences with the initialization of the
data pointer by the load-data-pointer command (see
an arriving data byte is stored at the display RAM address indicated by the data pointer.
The filling order is shown in
After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode:
If an I
The data pointer should be re-written prior to further RAM accesses.
The storage of display data is determined by the contents of the subaddress counter.
Storage is allowed only when the content of the subaddress counter match with the
hardware subaddress applied to A0, A1, and A2. The subaddress counter value is defined
by the device-select command (see
and the hardware subaddress do not match then data storage is inhibited but the data
pointer is incremented as if data storage had taken place. The subaddress counter is also
incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCF85176 occurs when the last RAM address is exceeded.
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character.
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In static drive mode the eight transmitted data bits are placed in row 0 of eight
successive 4-bit RAM words.
In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 of four successive 4-bit RAM words.
In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 to
three successive 4-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted.
In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 of two successive 4-bit RAM words.
In static drive mode by eight
In 1:2 multiplex drive mode by four
In 1:3 multiplex drive mode by three
In 1:4 multiplex drive mode by two
2
C-bus data access is terminated early then the state of the data pointer is unknown.
All information provided in this document is subject to legal disclaimers.
Rev. 01 — 14 April 2010
Figure
Figure
11:
11.
Table
12). If the content of the subaddress counter
Universal LCD driver for low multiplex rates
Table
11). Following this command,
PCF85176
© NXP B.V. 2010. All rights reserved.
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