pcf8832 NXP Semiconductors, pcf8832 Datasheet - Page 25
pcf8832
Manufacturer Part Number
pcf8832
Description
Pcf8832 Stn Rgb - 384 Output Column Driver
Manufacturer
NXP Semiconductors
Datasheet
1.PCF8832.pdf
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Philips Semiconductors
Table 8 N-line inversion (NLI[7:0] < 160)
Decoding of the blue bits is shown in Table 9. The data
byte for one pixel contains 8 bits (RRRGGGBB). The red
and green bits will be written directly to the RAM. For the
blue bits, the data to be written for B[1:0] values are
defined in the command register (address 0CH and 0DH).
The procedure for writing the blue bits is:
1. Program the blue scale register (ADR: 0CH and 0DH)
2. Send pixel information via interface; the pixel value via
3. Write procedure of pixel information to display RAM:
Table 9 Translation of blue bits
Table 10 Column output voltage ( V
2002 Aug 16
00000000 no n-line inversion (frame inversion)
00000001 inversion after each row
00000010 inversion after 2 rows
to
01100100 inversion after 100 rows
to
10011111 inversion after 159 rows
NLI[7:0]
STN RGB - 384 output column driver
e.g. set register 0CH to 01H.
interface is ADH, (RRR = 101), (GGG = 011) and
(B[1:0] = 01).
a) RRR and GGG is written directly to the RAM
b) The two blue bits decide which register bits are to
be used, in this example b012, b011 and b010 will
be written as blue pixel information to the display
RAM.
VPC[3:0]
b[1:0]
0000
1111
to
to
00
01
10
11
to
DESCRIPTION
REGISTER BITS
b002 b001 b000
b012 b011 b010
b102 b101 b100
b112 b111 b110
0CH and 0DH
COL
V
COL
= 100 mV)
2.5
4.0
to
(V)
25
Table 11 Set frame frequency
FFQ[4:0]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
FRAME FREQUENCY (Hz)
Preliminary specification
100
120
140
160
180
200
220
240
260
280
300
320
340
360
380
400
20
40
60
80
PCF8832
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