stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 23

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

III - FUNCTIONAL DESCRIPTION (continued)
III.2.1.3 - Description and Functions of the
- FLAG
- ABORT
- BIT STUFFING AND UNSTUFFING
- FRAME CHECK SEQUENCE
- ADDRESS RECOGNITION
The binary sequence 01111110marks the begin-
ning and the end of the HDLC Frame.
Note : In reception, three possible flag configura-
tions are allowed and correctly detected :
- two normal consecutive flags :
command.
In reception,seven consecutive1’s, inside a mes-
sage, are detected as an abort command and
generates an interrupt to the host.
In transmit direction, an abort is sent upon com-
mand of the micro-processor. No ending flag is
expected after the abort command.
This operation is done to avoid the confusion of
a data byte with a flag.
In transmission, if five consecutive 1’s appear in
the serial stream being transmitted,a zero isauto-
matically inserted (bit stuffing) after he fifth ”1”.
In reception, if five consecutive ”1” followed by a
zero are received, the ”0” is assumed to have
been inserted and is automatically deleted (bit
unstuffing).
TheFrame Check Sequenceiscalculatedaccording
to the recommendationQ921 of the CCITT.
In the frame, one or two bytes are transmitted to
indicate the destination of the message.
Two types of addresses are possible :
- a specific destination address
- a broadcast address.
In reception, the controller compares the receive
addresses to internal registers, which contain the
address message. 4 bits in the receive command
register (HRCR) inform the receiver of which
registers, it has to take into account for the com-
parison. The receiver compares the two address
bytes of the message to the specific board ad-
dress and the broadcast address. Upon an ad-
dress match, the address and the data following
are written to the data buffers; upon an address
mismatch, the frame is ignored. So, it authorizes
the filtering of the messages. If no comparison is
- two consecutive flags with a ”0” common :
- a global common flag : ...01111110...
this flag is the closing flag for the current frame
and the opening flag for the next frame
The binary sequence 1111111 marks an Abort
...0111111001111110...
...011111101111110...
HDLC Bytes
III.2.2 - CSMA/CR Capability
An HDLC channel can come in and go out by any
TDM input on the matrix. For time constraints,
direct HDLC Access is achieved by the input TDM
(DIN 8) and the output TDM (DOUT6).
In transmission, a time slot of a TDM can be shared
between different sources in Multi-point to point
configuration (different subscriber’s boards for ex-
ample). The arbitration system is the CSMA/CR
(Carrier Sense Multiple access with Contention
Resolution).
The contention is resolved by a bus connected to
the CB pin (Contention Bus). This bus is a 2Mbit/s
wire line common to all the potential sources.
If a Multi-HDLC has obtained the access to the bus,
the data to transmit is sent simultaneouslyon the CB
line and the outputTDM. Theresult of the contention
is readbackon the Echoline.If a collisionisdetected,
the transmission is stopped immediately. A conten-
tionon a bit basisis so achieved. Each message to
be sent with CSMA/CR has a priority class (PRI = 8,
10) indicated by the Transmit Descriptor and some
rules are implemented to arbitrate the access to the
line. The CSMA/CR Algorithm is given. When a
request to send a message occurs, the trans-
mitter determines if the shared channel is free. The
Multi-HDLC listens to the Echo line. If C or more
consecutive ”1” are detected (C depending on the
message’s priority), the Multi-HDLC begins to send
its message. Each bit sent is sampled back and
compared with the original value to send. If a bit is
different, the transmission is instantaneously
stopped (before the end of this bit time) and will
restart as soon as the Multi-HDLC will detect thatthe
channel is free without interrupting the microproc-
essor.
After a successful transmission of a message, a
programmablepenalty PEN(1 or 2) isapplied to the
transmitter (see Paragraph HDLC Transmit Com-
mand Register on Page 65). It guaranteesthat the
same transmitterwill not take the bus another time
before a transmitter which has to send a message
of same priority.
In case of a collision, the frame which has been
aborted is automatically retransmitted by the DMA
controller without warning the microprocessor of
this collision. The frame can be located in several
buffers in external memory. The collision can be
detected from the second bit of the opening frame
to the last but one bit of the closing frame.
specified, each frame is received whatever its
address field.
In Transmission, the controller sends the frame in-
cluding the destination or broadcastaddresses.
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