stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 78

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5464
IX - EXTERNAL REGISTERS (continued)
IX.3.2 - Bits written by the Rx DMAC only
CFT
ABT
UND
IX.3.3 - Transmit Buffer
Each transmit buffer is defined by its transmit descriptor.
The maximum size of the buffer is 2048 words (1 word=2 bytes)
IX.4 - Receive & Transmit HDLC Frame Interrupt
This word is located in the HDLC interrupt queue ; IQSR Register indicates the size of this HDLC interrupt
queue located in the external memory.
NS
Transmitter
Tx
A4/0
RRLF : Ready to Repeat Last Frame
EOQ
HALT : The TransmitDMAController hasreceivedHALT from the microprocessor; it is waiting”Continue”
BE
CFT
78/83
NBT is even : x = NBT - 2
bit15
NBT is odd : x = NBT - 1
NS
: Frame correctly transmitted
: Frame Transmitting Aborted
: Underrun
TBA + x ;
: New Status.
: Tx = 1, Transmitter
: Tx HDLC Channel 0 to 31
: End of Queue
: Buffer Empty
: Correctly Frame Transmitted
0
TBA
CFT = 1, the Frame has been correctly transmitted.
CFT = 0, the Frame has not been correctly transmitted.
ABT = 1, the frame has been aborted by the microprocessor during the transmission.
ABT = 0, the microprocessor has not aborted the frame during the transmission.
UND = 1, the transmit FIFO has not been fed correctly during the transmission.
UND = 0, the transmit FIFO has been fed correctly during the transmission.
Before writing the features of event in the external memory the Interrupt Controller reads the
NS bit :
if NS = 0, the Interrupt Controller puts this bit at ‘1’ when it writes the status word of the frame
which has been transmitted or received.
if NS = 1, the Interrupt Controller puts ICOV bit at ‘1’ to generate an interrupt (IR Register).
When the microprocessor has read the status word, it puts this bit at ‘0’ to acknowledge the new
status. This location becomes free for the Interrupt Controller.
In consequenceof event suchas Abort Command HDLC, Controller is waiting Start or Continue.
The Transmit DMA Controller (or the Receive DMA Controller) has encountered the current
Descriptor with EOQ at ”1”. DMA Controller is waiting ”Continue” from microprocessor.
from microprocessor.
If BINT bit of Transmit Descriptor is at ‘1’, the Transmit DMA Controller puts BE at ”1” when the
buffer has been emptied.
A frame has been transmitted. This status is provided only if BINT bit of Transmit Descriptor is
at ‘1’. CFT is located in the last descriptor if several descriptors are used to define a frame.
Tx
A4
A3
15
A2
A1
bit8
A0
bit7
0
0
First Word to Transmit
Last Word to Transmit
0
CFT/CFR BE/BF HALT
EOQ RRLF/ERF
bit 0
0