stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 77

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

IX - EXTERNAL REGISTERS (continued)
IX.3 - Transmit Descriptor
This transmit descriptor is located in shared memory. The quantity of descriptors is limited by the memory
size only.
The 5 first words located in shared memory to TDA+00 from TDA+08 are written by the microprocessor
and read by the DMAC only. The 6th word located in shared memory in TDA+10 is written by the DMAC
only during the frame reception and read by the microprocessor.
NBT
TBA
TDA
NTDA : Next Transmit Descriptor Address. LSB of NTDA Low is at Zero mandatory.
IX.3.1 - Bits written by the Microprocessor only
BINT
BOF
EOF
EOQ
CRCC : CRC Corrupted
PRI
TDA+00
TDA+02
TDA+04
TDA+06
TDA+08
TDA+10
: Number of Bytes to be transmitted (up to 4096).
: Transmit Buffer Address. LSB of TBA Low is at Zero mandatory.
: Transmit Descriptor Address.
: Interrupt at the end of the frame or when the buffer is become empty.
: Beginning Of Frame
: End Of Frame
: End Of Queue
: Priority Class 8 or 10
BINT = 1,
if EOF = 1 the DMAC generates an interrupt when the frame has been transmitted ;
if EOF = 0 the DMAC generates an interrupt when the buffer is become empty.
BINT = 0, the DMAC does not generate an interrupt during the transmission of the frame.
BOF = 1,the transmit bufferassociated to this transmit descriptor containsthe beginningof frame.
BOF = 0,the transmit buffer associated to this transmitdescriptor does not contain the beginning
of frame.
EOF = 1,the transmit buffer associated to this transmit descriptor contains the end of frame.
EOF = 0,the transmit buffer associated to this transmit descriptor does not contain the end of
frame.
EOQ = 1, the DMAC stops immediately its transmission, generates an interrupt (HDLC = 1 in
IR) and waits a command from the HTCR (HDLC Transmit Command Register).
EOQ = 0, the DMAC continues.
CRCC = 1,at the end of this frame the CRC will be corrupted by the Tx HDLC Controller.
PRI = 1, if CSMA/CR is validated for this channel, the priority class is 8.
PRI = 0, if CSMA/CR is validated for this channel the priority class is 10.
(see Register CSMA)
BINT
CFT
15
BOF
ABT
14
UND
EOF
Not used
13
Not used
EOQ
12
Next Transmit Descriptor Address Low (16 bits)
11
Transmit Buffer Address Low (16 bits)
10
CRC
C
9
Number of Bytes to be Transmitted (NBT)
PRI
8
7
6
5
NTDA High (8 bits)
TBA High (8 bits)
4
3
2
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