stlc5464 STMicroelectronics, stlc5464 Datasheet - Page 24

• Manufacturer Part Number: stlc5464
• Description: Multi-hdlcwith Switching Matrix Associated
• Manufacturer: STMicroelectronics

STLC5464
III - FUNCTIONAL DESCRIPTION (continued)
III.2.3 - Time Slot Assigner Memory
Each HDLC channel is bidirectional and configu-
rate by the Time Slot Assigner (TSA).
The TSAis a memoryof 32 words (one per physical
Time Slot) where all of the 32 input and output time
slots of the HDLC controllers can be associated
to logical HDLC channels. Super channels are
created by assigning the same logical channel
number to several physical time slots.
The following features are configurate for each
HDLC time slot :
- Time slot used or not
- One logical channel number
- Its source : (DIN 8 or the output 7 of the matrix)
- Its bit rate and concerned bits (4kbit/s to
- Its destination :
III.2.4 - Data Storage Structure
Data associated with each Rx and Tx HDLC chan-
nel is stored in externalmemory; The data transfers
between the HDLC controllers and memory are
ensuredby 32 DMAC(Direct Memory AccessCon-
troller) in reception and 32 DMAC in transmission.
The storage structure chosen in both directions is
composed of one circular queue of buffers per
channel. In such a queue, each data buffer is
pointed to by a Descriptor located in external mem-
ory too. The main information contained in the
Descriptor is the address of the Data Buffer, its
length and the address of the next Descriptor; so
the descriptors can be linked together.
This structure allows to :
- Store receive frames of variable and unknown
- Read transmit frames stored in external memory
- Easily perform the frame relay function.
24/83
64kbit/s). 4kbit/s correspond to one bit transmit-
ted each two frames. This bit must be present in
two consecutive frames in reception, and re-
peated twice in transmission.
- direct output on DOUT6
- direct output on DOUT6 and on the Contention
- on another OTDM via input 7 of the matrix and
length
by the host
Bus (CB)
on the Contention Bus (CB)
III.2.4.1 - Reception
At the initialization of the application, the host has
to prepare an Initialization Block memory, which
contains the first receive buffer descriptor address
for each channel, and the receive circular queues.
At the opening of a receive channel, the DMA
controller reads the address of the first buffer de-
scriptor corresponding to this channel in the initiali-
zation Block. Then, the data transfer can occur
without intervention of the processor (see Figure 9
on Page 25).
A new HDLC frame always begins in a new buffer.
A long frame can be split between several buffers
if the buffer size is not sufficient. All the information
concerning the frame and its location in the
circular queue is included in the Receive Buffer
Descriptor :
- The Receive Buffer Address (RBA),
- The size of the receive buffer (SOB),
- The number of byteswritten into the buffer (NBR),
- The Next Receive Descriptor Address (NRDA),
- The status concerning the receive frame,
- The control of the queue.
III.2.4.2 - Transmission
In transmission, the data is managed by a similar
structure as in reception (see Figure 10 on
Page 25).
By the same way, a frame can be split up between
consecutive transmit buffers.
The main information contained in the Transmit
Descriptor are :
- transmit buffer address (TBA),
- numberof bytes to transmit(NBT) concerningthe
- next transmit descriptor address (NTDA),
- status of the frame after transmission,
- control bit of the queue,
- CSMA/CR priority (8 or 10).
III.2.4.3 - Frame Relay
The principle of the frame relay is to transmit a
frame which has been received without treatment.
A new heading is just added. This will be easily
achieved, taking into account that the queue struc-
ture allows the transmission of a frame split be-
tween several buffers.
buffer,