adc081c027cimkx National Semiconductor Corporation, adc081c027cimkx Datasheet - Page 14

• Manufacturer Part Number: adc081c027cimkx
• Description: I2c-compatible, 12-bit Analog-to-digital Converter Adc With Alert Function
• Manufacturer: National Semiconductor Corporation

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1.0 Functional Description
The ADC081C021 and the ADC081C027 are successive-ap-
proximation analog-to-digital converters designed around a
charge-redistribution digital-to-analog converter. Unless oth-
erwise stated, references to the ADC081C021 in this section
will apply to both the ADC081C021 and the ADC081C027.
1.1 CONVERTER OPERATION
Simplified schematics of the ADC081C021 in both track and
hold operation are shown in Figure 2 and Figure 3 respec-
tively. In Figure 2, the ADC081C021 is in track mode. SW1
connects the sampling capacitor to the analog input channel
and SW2 equalizes the comparator inputs. The ADC is in this
state for approximately 0.4µs at the beginning of every con-
version cycle, which begins at the ACK fall of SDA. Conver-
sions occur when the conversion result register is read and
when the ADC is in automatic conversion mode. (see Section
1.9 AUTOMATIC CONVERSION MODE).
Figure 3 shows the ADC081C021 in hold mode. SW1 con-
nects the sampling capacitor to ground and SW2 unbalances
the comparator. The control logic then instructs the charge-
redistribution DAC to add or subtract fixed amounts of charge
to or from the sampling capacitor until the comparator is bal-
anced. When the comparator is balanced, the digital word
supplied to the DAC is also the digital representation of the
analog input voltage. This digital word is stored in the con-
version result register and read via the 2-wire interface.
In the Normal (non-Automatic) Conversion mode, a new con-
version is started after the previous conversion result is read.
In the Automatic Mode, conversions are started at set inter-
vals, as determined by bits D7 through D5 of the Configuration
Register. The intent of the Automatic mode is to provide a
"watchdog" function to ensure that the input voltage remains
within the limits set in the Alert Limit Registers. The minimum
and maximum conversion results can then be read from the
Lowest Conversion Register and the Highest Conversion
Register, as described in Section 1.6 INTERNAL REGIS-
TERS.
FIGURE 2. ADC081C021 in Track Mode
FIGURE 3. ADC081C021 in Hold Mode
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1.2 ANALOG INPUT
An equivalent circuit for the input of the ADC081C021 is
shown in Figure 4. The diodes provide ESD protection for the
analog input. The operating range for the analog input is 0 V
to V
conduct and result in erratic operation. For this reason, these
diodes should NOT be used to clamp the input signal.
The capacitor C1 in Figure 4 has a typical value of 3 pF and
is mainly the package pin capacitance. Resistor R1 is the on
resistance (R
is typically 500Ω. Capacitor C2 is the ADC081C021 sampling
capacitor, and is typically 30 pF. The ADC081C021 will de-
liver best performance when driven by a low-impedance
source (less than 100Ω). This is especially important when
using the ADC081C021 to sample dynamic signals. A buffer
amplifier may be necessary to limit source impedance. Use a
precision op-amp to maximize circuit performance. Also im-
portant when sampling dynamic signals is a band-pass or low-
pass filter to reduce noise at the input.
The analog input is sampled for eight internal clock cycles, or
for typically 400 ns, after the fall of SDA for acknowledgement.
This time could be as long as about 530 ns. The sampling
switch opens and the conversion begins this time after the fall
of ACK. This time are typical at room temperature and may
vary with temperature.
1.3 ADC TRANSFER FUNCTION
The output format of the ADC081C021 is straight binary.
Code transitions occur midway between successive integer
LSB values. The LSB width for the ADC081C021 is V
The ideal transfer characteristic is shown in Figure 5. The
transition from an output code of 0000 0000 0000 to a code
of 0000 0000 0001 is at 1/2 LSB, or a voltage of V
Other code transitions occur at intervals of 1 LSB.
A
. Going beyond this range will cause the ESD diodes to
FIGURE 5. Ideal Transfer Characteristic
FIGURE 4. Equivalent Input Circuit
ON
) of the multiplexer and track / hold switch and
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A
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