adc081c027cimkx National Semiconductor Corporation, adc081c027cimkx Datasheet - Page 18

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adc081c027cimkx

Manufacturer Part Number
adc081c027cimkx
Description
I2c-compatible, 12-bit Analog-to-digital Converter Adc With Alert Function
Manufacturer
National Semiconductor Corporation
Datasheet

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1.6.6 V
This register holds the upper limit threshold used to determine the alert condition. If the conversion moves higher than this limit, a
V
Pointer Address 04h (Read/Write)
Default Value: 0FFFh
1.6.7 V
This register holds the hysteresis value used to determine the alert condition. After a V
result must move within the V
in the configuration register, alert conditions will not self-clear.
Pointer Address 05h (Read/Write)
Default Value: 0000h
1.6.8 V
This register holds the Lowest Conversion result when in the automatic conversion mode. Each conversion result is compared
against the contents of this register. If the value is lower, it becomes the lowest conversion and replaces the current value. If the
value is higher, the register contents remain unchanged. The lowest conversion value can be cleared at any time by writing 0FFFh
to this register. The value of this register will update automatically when the automatic conversion mode is enabled, but is NOT
updated in the normal mode.
Pointer Address 06h (Read/Write)
Default Value: 0FFFh
Bits
15:12
11:4
3:0
Bits
15:12
11:4
3:0
HIGH
D15
D15
D15
D7
D7
D7
alert is generated.
HIGH
HYST
MIN
Name
Reserved
V
Reserved
Name
Reserved
Hysteresis
Reserved
-- Lowest Conversion Register
HIGH
-- Alert Limit Register - Over Range
-- Alert Hysteresis Register
Limit
Lowest Conversion [3:0]
D14
D14
D14
D6
D6
D6
V
Hysteresis [3:0]
HIGH
Reserved
Reserved
Reserved
HIGH
Limit [3:0]
Description
Always reads zeros. Zeros must be written to these bits.
Sets the upper limit threshold used to determine the alert condition. If the conversion moves
higher than this limit, a V
Always reads zeros. Zeros must be written to these bits.
Description
Always reads zeros. Zeros must be written to these bits.
Hysteresis value. D11 is MSB.
Always reads zeros. Zeros must be written to these bits.
or V
D13
D13
D13
LOW
D5
D5
D5
limit by more than this value to clear the alert condition. Note: If the Alert Hold bit is set
D12
D12
D12
D4
D4
D4
HIGH
alert is generated.
18
D11
D11
D11
D3
D3
D3
Lowest Conversion [7:4]
D10
D10
D10
D2
D2
D2
HIGH
V
Hysteresis [7:4]
HIGH
Reserved
Reserved
Reserved
or V
Limit [7:4]
LOW
alert occurs, the conversion
D9
D1
D9
D1
D9
D1
D8
D0
D8
D0
D8
D0

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