adc08d1500dev National Semiconductor Corporation, adc08d1500dev Datasheet
adc08d1500dev
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adc08d1500dev Summary of contents
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... Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Indus- ≤ ≤ trial (-40°C T +85°C) temperature range. A Block Diagram © 2007 National Semiconductor Corporation Features ■ Internal Sample-and-Hold ■ Single +1.9V ±0.1V Operation ■ Choice of SDR or DDR output clocking ■ ...
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Ordering Information Industrial Temperature Range (-40°C < T ADC08D1500CIYB ADC08D1500EVAL Pin Configuration * Exposed pad on back of package must be soldered to ground plane to ensure rated performance. www.national.com < +85°C) A 128-Pin Exposed Pad LQFP Evaluation Board 2 ...
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Pin Descriptions and Equivalent Circuits Pin Functions Pin No. Symbol Equivalent Circuit 3 OutV / SCLK OutEdge / DDR / 4 SDATA 15 DCLK_RST PDQ 30 CAL 14 FSR/ECE CalDly / DES / 127 SCS Description Output ...
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Pin Functions Pin No. Symbol 18 CLK+ 19 CLK I− Q− CMO 126 CalRun 32 R EXT 34 Tdiode_P ...
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Pin Functions Pin No. Symbol Equivalent Circuit DI7− / DQ7− DI7+ / DQ7 DI6− / DQ6− DI6+ / DQ6 DI5− / DQ5− ...
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Pin Functions Pin No. Symbol 42, 53, 64, 74, 87, 97, DR GND 108, 119 52, 63, 98, NC 109, 120 www.national.com Equivalent Circuit Ground return for V No Connection. Make no connection to these pins. 6 Description . DR ...
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Absolute Maximum Ratings (Notes Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage on Any Input Pin Ground Difference |GND ...
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Symbol Parameter 2nd Harm Second Harmonic Distortion 3rd Harm Third Harmonic Distortion SFDR Spurious-Free dynamic Range IMD Intermodulation Distortion Out of Range Output Code (In addition to OR Output high) INTERLEAVE MODE (DES Pin 127=Float) - DYNAMIC CONVERTER CHARACTERISTICS FPBW ...
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Symbol Parameter Maximum Bandgap Reference C V LOAD BG load Capacitance TEMPERATURE DIODE CHARACTERISTICS ΔV Temperature Diode Voltage BE CHANNEL-TO-CHANNEL CHARACTERISTICS Offset Match Positive Full-Scale Match Negative Full-Scale Match Phase Matching (I,Q) Crosstalk from I (Agressor X-TALK (Victim) ...
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Symbol Parameter I Output Driver Supply Current DR P Power Consumption D D.C. Power Supply Rejection PSRR1 Ratio A.C. Power Supply Rejection PSRR2 Ratio AC ELECTRICAL CHARACTERISTICS f Maximum Input Clock Frequency Normal Mode (non DES) or DES Mode CLK1 ...
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Symbol Parameter PD low to Rated Accuracy t WU Conversion (Wake-Up Time) f Serial Clock Frequency SCLK t Data to Serial Clock Setup Time (Note 11) SSU t Data to Serial Clock Hold Time SH Serial Clock Low Time Serial ...
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Specification Definitions APERTURE (SAMPLING) DELAY is that time required after the fall of the clock input for the sampling switch to open. The Sample/Hold circuit effectively stops capturing the input sig- nal and goes into the “hold” mode the aperture ...
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SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or SINAD) is the ratio, expressed in dB, of the rms value of the input signal at the output to the rms value of all of the other spectral components below half the input ...
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Transfer Characteristic www.national.com FIGURE 2. Input / Output Transfer Characteristic 14 20152122 ...
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Timing Diagrams FIGURE 3. ADC08D1500 Timing — SDR Clocking FIGURE 4. ADC08D1500 Timing — DDR Clocking 15 20152114 20152159 www.national.com ...
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FIGURE 7. Clock Reset Timing in SDR Mode with OUTEDGE Low www.national.com FIGURE 5. Serial Interface Timing FIGURE 6. Clock Reset Timing in DDR Mode 16 20152119 20152120 20152123 ...
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FIGURE 8. Clock Reset Timing in SDR Mode with OUTEDGE High FIGURE 9. Self Calibration and On-Command Calibration Timing 17 20152124 20152125 www.national.com ...
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Typical Performance Characteristics INL vs CODE DNL vs. CODE POWER DISSIPATION vs. SAMPLE RATE www.national.com V =V =1.9V, F =1500MHz CLK INL vs TEMPERATURE 20152164 DNL vs. TEMPERATURE 20152166 ENOB vs. TEMPERATURE 20152181 18 =25°C unless otherwise ...
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ENOB vs. SUPPLY VOLTAGE 20152177 ENOB vs. INPUT FREQUENCY 20152179 SNR vs. SUPPLY VOLTAGE 20152169 ENOB vs. SAMPLE RATE SNR vs. TEMPERATURE SNR vs. SAMPLE RATE 19 20152178 20152168 20152170 www.national.com ...
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SNR vs. INPUT FREQUENCY THD vs. SUPPLY VOLTAGE THD vs. INPUT FREQUENCY www.national.com THD vs. TEMPERATURE 20152171 THD vs. SAMPLE RATE 20152173 SFDR vs. TEMPERATURE 20152175 20 20152172 20152174 20152185 ...
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SFDR vs. SUPPLY VOLTAGE 20152184 SFDR vs. INPUT FREQUENCY 20152183 Spectral Response at FIN = 745 MHZ 20152188 SFDR vs. SAMPLE RATE Spectral Response at FIN = 373 MHZ CROSSTALK vs SOURCE FREQUENCY 21 20152182 20152187 20152163 www.national.com ...
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FULL POWER BANDWIDTH www.national.com 20152186 22 ...
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Functional Description The ADC08D1500 is a versatile A/D Converter with an inno- vative architecture permitting very high speed operation. The controls available ease the application of the device to circuit solutions. Optimum performance requires adherence to the provisions discussed ...
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It is important that the input signals are either a.c. coupled to the inputs with the V pin grounded, or d.c. coupled with CMO the V pin left floating. An input common mode voltage CMO equal to the V ...
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If the LVDS lines are long and/or the system in which the ADC08D1500 is used is noisy, it may be necessary to tie the OutV pin high. The LVDS data output have a typical common mode voltage of ...
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The default state of the Extended Control Mode is set upon power-on reset (internally performed by the device) and is shown in Table 3. TABLE 3. Extended Control Mode Operation (Pin 14 Floating) Extended Control Mode Feature SDR or DDR ...
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TABLE 4. Register Addresses 4-Bit Address Loading Sequence: A3 loaded after H0, A0 loaded last Hex ...
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I-Channel Offset Addr: 2h (0010b) D15 D14 D13 D12 D11 (MSB) Offset Value Sign Bits 15:8 Offset Value. The input offset of the I-Channel ADC is adjusted linearly and monotonically by ...
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DES Enable Addr: Dh (1101b) W only (0x3FFF) D15 D14 D13 D12 D11 D10 DEN ACP Bit 15 DES Enable. Setting this bit to ...
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Note Regarding Extended Mode Offset Correction When using the channel Offset Adjust registers, the following information should be noted. For offset values of +0000 0000 and -0000 0000, the actual offset is not the same. By ...
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Do not connect an unused analog input to ground. 20152144 FIGURE 11. Differential Input Drive When the d.c. coupled mode is used, a common mode volt- age must be provided at the differential inputs. This common mode voltage ...
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Electrical Characteristics Table. The clock in- puts are internally terminated and biased. The input clock signal must be capacitively coupled to the clock pins as indi- cated ...
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To initiate an on-command calibration, bring the CAL pin high for a minimum of 80 input clock cycles after it has been low for a minimum of 80 input clock cycles. Holding the CAL pin high upon power up will ...
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THE DIGITAL OUTPUTS The ADC08D1500 demultiplexes the output data of each of the two ADCs on the die onto two LVDS output buses (total of four buses, two for each ADC). For each of the two con- verters, the ...
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To maximize the removal of heat from the package, a thermal land pattern must be ...
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Non-Extended Control Mode Operation Non-extended control mode operation means that the Serial Interface is not active and all controllable functions are con- trolled with various pin settings. That is, the full-scale range and input coupling (a.c. or d.c.) are ...
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Physical Dimensions inches (millimeters) unless otherwise noted NOTES: UNLESS OTHERWISE SPECIFIED REFERENCE JEDEC REGISTRATION MS-026, VARIATION BFB. 128-Lead Exposed Pad LQFP Order Number ADC08D1500CIYB NS Package Number VNX128A 37 www.national.com ...
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