adc08d1500dev National Semiconductor Corporation, adc08d1500dev Datasheet - Page 11

• Manufacturer Part Number: adc08d1500dev
• Description: High Performance, Low Power, Dual 8-bit, 1.5 Gsps A/d Converter
• Manufacturer: National Semiconductor Corporation

t
f
t
t
t
t
t
t
t
WU
SCLK
SSU
SH
CAL
CAL_L
CAL_H
CalDly
CalDly
Symbol
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum
Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than V
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two. This limit is not placed upon the power, ground and digital output pins.
Note 4: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 5: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.
Note 6: The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
Note 7: To guarantee accuracy, it is required that V
achieving rated performance requires that the backside exposed pad be well grounded.
Note 8: Typical figures are at T
Level).
Note 9: Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,
therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 2. For relationship between Gain Error and Full-Scale Error, see
Specification Definitions for Gain Error.
Note 10: The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to
ground are isolated from the die capacitances by lead and bond wire inductances.
Note 11: This parameter is guaranteed by design and is not tested in production.
Note 12: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 13: The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die
capacitances by lead and bond wire inductances.
Note 14: Each of the two converters of the ADC08D1500 has two LVDS output buses, which each clock data out at one half the sample rate. The data at each
bus is clocked out at one half the sample rate. The second bus (D0 through D7) has a pipeline latency that is one Input Clock cycle less than the latency of the
first bus (Dd0 through Dd7).
Note 15: Tying V
supply rail will also affect the differential LVDS output voltage (V
PD low to Rated Accuracy
Conversion (Wake-Up Time)
Serial Clock Frequency
Data to Serial Clock Setup Time (Note 11)
Data to Serial Clock Hold Time
Serial Clock Low Time
Serial Clock High Time
Calibration Cycle Time
CAL Pin Low Time
CAL Pin High Time
Calibration delay determined by
pin 127
Calibration delay determined by
pin 127
BG
to the supply rail will increase the output offset voltage (V
Parameter
A
= 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
A
and V
(Note 11)
(Note 11)
See Figure 9 (Note 11)
See Figure 9 (Note 11)
See Section 1.1.1, Figure 9,
(Note 11)
See Section 1.1.1, Figure 9,
(Note 11)
DR
be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,
OD
), causing it to increase by 40mV (typical).
Conditions
OS
11
) by 400mv (typical), as shown in the V
20152104
1.4 x 10
(Note 8)
Typical
500
100
2.5
1
A
), the current at that pin should be limited to
OS
5
specification above. Tying V
(Note 8)
Limits
2
2
80
80
4
4
25
31
Clock Cycles
Clock Cycles
Clock Cycles
Clock Cycles
Clock Cycles
www.national.com
(Limits)
ns (min)
ns (min)
ns (min)
ns (min)
Units
(max)
(min)
(min)
(min)
MHz
ns
BG
to the