adc08d1500dev National Semiconductor Corporation, adc08d1500dev Datasheet - Page 27

• Manufacturer Part Number: adc08d1500dev
• Description: High Performance, Low Power, Dual 8-bit, 1.5 Gsps A/d Converter
• Manufacturer: National Semiconductor Corporation

1.4 REGISTER DESCRIPTION
Eight write-only registers provide several control and config-
uration options in the Extended Control Mode. These regis-
ters have no effect when the device is in the Normal Control
Mode. Each register description below also shows the Power-
On Reset (POR) state of each control bit.
Bit 15
Bit 14
Bit 13
A3
Addr: 1h (0001b)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D15
D7
1
1
A2
D14
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
D6
0
1
A3 loaded after H0, A0 loaded last
Must be set to 1b
Must be set to 0b
Must be set to 1b
TABLE 4. Register Addresses
D13
Configuration Register
D5
A1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
Loading Sequence:
4-Bit Address
DCS DCP
D12
D4
1
A0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
D11
D3
1
Hex
Ah
Bh
Ch
Dh
Eh
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Fh
nDE
D10
D2
Register Addressed
W only (0xB2FF)
DES Coarse Adjust
1
"Q" Ch Full-Scale
"I" Ch Full-Scale
DES Fine Adjust
Voltage Adjust
Voltage Adjust
"Q" Ch Offset
Configuration
"I" Ch Offset
DES Enable
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OV
D9
D1
1
OE
D8
D0
1
27
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Bits 7:0
DCS:Duty Cycle Stabilizer. When this bit is set
to 1b , a duty cycle stabilzation circuit is
applied to the clock input. When this bit is set
to 0b the stabilzation circuit is disabled.
POR State: 1b
DCP: DDR Clock Phase. This bit only has an
effect in the DDR mode. When this bit is set to
0b, the DCLK edges are time-aligned with the
data bus edges ("0° Phase"). When this bit is
set to 1b, the DCLK edges are placed in the
middle of the data bit-cells ("90° Phase"),
using the one-half speed DCLK shown in
Figure 4 as the phase reference.
POR State: 0b
nDE: DDR Enable. When this bit is set to 0b,
data bus clocking follows the DDR (Double
Data Rate) mode whereby a data word is
output with each rising and falling edge of
DCLK. When this bit is set to a 1b, data bus
clocking follows the SDR (single data rate)
mode whereby each data word is output with
either the rising or falling edge of DCLK , as
determined by the OutEdge bit.
POR State: 0b
OV: Output Voltage. This bit determines the
LVDS outputs' voltage amplitude and has the
same function as the OutV pin that is used in
the normal control mode. When this bit is set
to 1b, the standard output amplitude of 710
mV
reduced output amplitude of 510 mV
used.
POR State: 1b
OE: Output Edge. This bit selects the DCLK
edge with which the data words transition in
the SDR mode and has the same effect as the
OutEdge pin in the normal control mode.
When this bit is 1, the data outputs change with
the rising edge of DCLK+. When this bit is 0,
the data output change with the falling edge of
DCLK+.
POR State: 0b
Must be set to 1b.
P-P
is used. When this bit is set to 0b, the
www.national.com
P-P
is