tda8757a NXP Semiconductors, tda8757a Datasheet - Page 14

• Manufacturer Part Number: tda8757a
• Description: Tda8757a Triple 8-bit Adc 205 Msps
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09549
Preliminary data
Fig 7. Definition of odd and even pixels; Edge = 0, Dmx = 0 and Ckrp = 1.
CKREFO
CKADC
CKREF
OUT A
8.2.3 ADCs
8.2.4 Data outputs
8.2.5 PLL
Three ADCs convert analog signals into three series of 8-bit codes, with a maximum
clock frequency of 205 Msps. The ADCs input range is 1 V (p-p) full-scale and the
pipeline delay is 1 clock cycle from the sampling to the data output. The reference
ladders regulators are integrated.
ADC outputs are straight binary. Pin OE enables to switch the output status between
active and high-impedance (OE = HIGH). It is possible to force the outputs with a
maximum 10 pF capacitive load. The timing must be checked very carefully if the
capacitive loads are more than 10 pF.
It is possible to force the outputs to logic 0 during the gain calibration (during HSYNC
pulse) and during the clamping (CLP pulse). This mode is activated through the serial
interface by setting bit ‘Blk’ to logic 1 in register DEMUX.
The TDA8757A provides outputs either on one port (port A) or on two ports (ports A
and B). The selection is made with the serial interface by setting bit ‘Dmx’ to logic 0 or
logic 1 in register DEMUX. When just one port is used (Dmx = 0), the unused ports
are forced to LOW level. When two ports are used (Dmx = 1), it is possible to select
the port that would provide the odd pixel by setting bit ‘Odda’ to logic 1 or logic 0 in
register DEMUX; when this bit is logic 1, odd pixel on output of port A.
One out-of-range bit exists per channel (OR
when the signal is out-of-range of the ADC voltage ladder.
Finally, two configurations are possible: either the port A outputs and the port B
outputs are both synchronous or they are interleaved. The selection is done by
setting bit ‘Shift’ to logic 0 or logic 1 in register DEMUX.
The ADCs are clocked by either the internal PLL locked to the reference clock
CKREF or an external clock connected to pin CKEXT. All parts of the PLL are on-chip
except the loop filter capacitance. The selection is performed via the serial interface
by setting bit ‘Ckext’ in register PHASE (Ckext = 1 when the external clock is used).
XXX
Rev. 01 — 22 March 2002
XXX
R
ODD
, OR
G
and OR
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Triple 8-bit ADC 205 Msps
B
). It will be at logic 1
EVEN
TDA8757A
FCE708
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