tda8757a NXP Semiconductors, tda8757a Datasheet - Page 20

• Manufacturer Part Number: tda8757a
• Description: Tda8757a Triple 8-bit Adc 205 Msps
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09549
Preliminary data
9.1.5 VCO register
9.1.6 Divider register
9.1.7 Phase register
Bits ‘Z2’, ‘Z1’ and ‘Z0’ enable the internal resistance for the VCO filter to be selected.
Table 9:
Bits ‘Vco1’ and ‘Vco0’ control the VCO gain.
Table 10: VCO gain control
The default programmed value is as follows:
This register controls the PLL frequency. Bits ‘Di8’ to ‘Di0’ are the LSB bits. The
default programmed value is 0110 1001 1000 = 1688.
The MSB bits (‘Di11’, ‘Di10’ and ‘Di9’) and the LSB bit ‘Di0’ have to be programmed
before bits ‘Di8’ to ‘Di1’ in order to have the required divider ratio. Bit ‘Di0’ is used for
the parity divider number (Di0 = 0: even number; Di0 = 1: odd number). It should be
noted that if the I
toggled, then the registers have to be loaded twice to have the update divider ratio.
Bit ‘Ckext’ is logic 0 when the used clock is the PLL clock and logic 1 when the used
clock is the external clock.
Bit ‘Ckrs’ is logic 1 when the synchronization is done with CKREF (see
Bits ‘P4’ to ‘P0’ are used to program the phase shift for clock CKDATA.
Z2
0
0
0
0
1
1
1
1
Vco1
0
0
1
1
•
•
Internal resistance = 2.25 k
VCO gain = 70 MHz/V.
VCO register bits
2
C-bus programming is done in mode 1 and the bit ‘Di0’ has to be
Rev. 01 — 22 March 2002
Z1
0
0
1
1
0
0
1
1
Vco0
0
1
0
1
Z0
0
1
0
1
0
1
0
1
VCO gain (MHz/V)
20
30
60
115
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
Triple 8-bit ADC 205 Msps
TDA8757A
Resistance (k )
high-impedance
9
6.4
4.5
3.2
2.25
1.6
1.1
Pixel clock
frequency range
(MHz)
12 to 28
28 to 55
55 to 115
115 to 205
Figure
3).
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