tda8757a NXP Semiconductors, tda8757a Datasheet - Page 19

• Manufacturer Part Number: tda8757a
• Description: Tda8757a Triple 8-bit Adc 205 Msps
• Manufacturer: NXP Semiconductors

Philips Semiconductors
9397 750 09549
Preliminary data
9.1.4 Control register
To modulate this gain, the fine register is programmed using the above equation. With
a full-scale ADC input, the fine register resolution is a
Table 7
Table 7:
The default programmed value is: N
COAST and HSYNC signals can be derived by setting the I
and ‘Hlevel’ respectively. When bits ‘Vlevel’ and ‘Hlevel’ are set to zero, COAST and
HSYNC are active HIGH.
Bit ‘Edge’ defines the rising or falling edge of CKREF to synchronize the PLL. It will
be on the rising edge if the bit is a logic 0 and on the falling edge if the bit is at logic 1.
Bits ‘Up’ and ‘Do’ are used for the test, to force the charge pump current. These bits
have to be logic 0 during normal use.
Bit ‘Cken’ is used for the test to check the CKADC internal signal. This bit has to be
logic 0 during normal use.
Bits ‘Ip0’, ‘Ip1’ and ‘Ip2’ control the charge pump current, to increase the bandwidth of
the PLL, as shown in
Table 8:
The default programmed value is as follows:
N
0
31
Ip2
0
0
0
0
1
1
1
1
•
•
•
•
FINE
Charge pump current = 700 A
Bits ‘Up’ and ‘Do’ are used for testing, normally they are set to logic 0
Rising edge of CKREF: bit ‘Edge’ at logic 0
COAST and HSYNC inputs are active HIGH: bits ‘Vlevel’ and ‘Hlevel’ at logic 0.
for N
Typical gain correspondence (FINE)
Charge pump current control
COARSE
Rev. 01 — 22 March 2002
= 32).
Table
Ip1
0
0
1
1
0
0
1
1
8.
Gain
0.825
0.878
FINE
= 0.
Ip0
0
1
0
1
0
1
0
1
© Koninklijke Philips Electronics N.V. 2002. All rights reserved.
1
2
LSB peak-to-peak (see
V
1.212
1.139
Triple 8-bit ADC 205 Msps
2
i
to be full-scale (V)
C-bus control bits ‘Vlevel’
TDA8757A
Current ( A)
6.25
12.5
25
50
100
200
400
700
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